Dine and Learn: DSP for FPGA
The Denver Section would like to invite you to join us for the latest presentation in our Dine and Learn series!
Come join your fellow IEEE members and local engineers for a fun filled evening of appetizers, networking, and dinner, while we discover exciting new innovations in technology. Once a month one of your local Denver IEEE Societies will host the event and bring in a unique speaker related to their field to present. This provides you, our members, with a unique opportunity to explore and learn about exciting new technologies being developed around you. Early on in the evening you’ll also have ample opportunity to mingle with your fellow engineers and colleagues delving into a broad range of technical expertise.
We will provide the appetizers, but dinner is at your own expense. Dinner for students is free.
If there is a specific speaker or topic you find interesting please let us know and we will try to accommodate it in the schedule.
Upcoming presentations:
Novemeber - Small Satellites: Technology Challenges and Prospects for Improved Weather Forecasting
December - No event
January - TBD
Date and Time
Location
Hosts
Registration
- Date: 10 Oct 2017
- Time: 06:00 PM to 09:00 PM
- All times are (GMT-07:00) US/Mountain
- Add Event to Calendar
- 10633 Westminster Blvd
- #900
- Westminster, Colorado
- United States 80020
- Building: Rock Bottom Brewery
- Room Number: in the "Promenade Room"
- Click here for Map
- Starts 25 September 2017 12:00 AM
- Ends 10 October 2017 12:00 AM
- All times are (GMT-07:00) US/Mountain
- 0 in-person spaces left!
- No Admission Charge
Speakers
Mark Moyer of DSP in FPGA
DSP - FPGA Compute Processing Technology & Workflows
Beginning with the inclusion of simple multiplier blocks at the 130nM process node, FPGA compute hardware solutions have continually evolved becoming more capable, flexible, and scalable with each generation. These embedded compute elements, together with high density RAM elements, flexible logic modules, and ubiquitous interconnect support implementation of extremely compute intensive algorithms in a power efficient manner.
Growing FPGA compute capabilities provide more options for implementation and more options to manage data flow and for partitioning complex compute operations between hardware and software. Algorithm Developers, Software Programmers, Embedded Programmers and FPGA Hardware Engineers can all contribute to this process and tool chains are evolving to support this collaboration. Complex systems also must be verified which drives the need for a more unified flow that supports all phases of the development process. Higher level tools have evolved to the point where there are several alternatives from which to choose.
Biography:
Mark Moyer is a Field Applications Engineer with Intel Corporation providing local and remote support to worldwide Intel customers developing FPGA based designs for the Data Center, Industrial, Communications, and Test and Measurement markets.
- Ten + years implementing analog, mixed signal and digital read/write channel and servo channel designs in data storage products.
- Fifteen years supporting FPGA design development for Altera and now Intel.
B.S. Electrical Engineering, University of Colorado Denver 1992
Mark Moyer of DSP in FPGA
DSP - FPGA Compute Processing Technology & Workflows
Biography:
Agenda
6:00 - 6:15 Registration and Appetizers
6:00 - 7:15 Dinner and Networking
7:30 - 9:00 Presentation
IEEE ---- Denver Section