IEEE CTS CAS/SSC Meeting: RF Harmonic Oscillators Integrated in Silicon Technologies

#Technical #talk
Share

Techinal Seminar by IEEE SSC DL



  Date and Time

  Location

  Hosts

  Registration



  • Date: 08 Feb 2018
  • Time: 10:00 AM to 11:30 AM
  • All times are (GMT-06:00) US/Central
  • Add_To_Calendar_icon Add Event to Calendar
  • 2501 Speedway
  • Austin, Texas
  • United States 78712
  • Building: EER
  • Room Number: 3.646
  • Click here for Map

  • Contact Event Host
  • See link to map above. Occasionally you might find street level parking for free -- but watch out for the parking signs and restrictions. Another place to park is SJG, the San Jacinto Garage -- after 6PM, it is $7 to park all night.

  • Co-sponsored by Nagaraja
  • Starts 15 November 2017 12:00 AM
  • Ends 08 February 2018 12:00 AM
  • All times are (GMT-06:00) US/Central
  • No Admission Charge


  Speakers

Topic:

RF Harmonic Oscillators Integrated in Silicon Technologies

Abstract: As one of the truly fundamental analog functions in any wireless/wireline application, the voltage-controlled oscillator keeps attracting a great deal of well-deserved attention. In this presentation, we will investigate the mechanisms of phase noise generation in harmonic oscillators, including some recently published general results, after which we will analyze both classical and emergent oscillator architectures, describing pros and cons for each. Various techniques to achieve a very wide oscillator tuning range will be illustrated as well.

Biography:

Pietro Andreani received the M.S.E.E. degree from the University of Pisa, Italy, in 1988, and the Ph.D. degree from Lund University, Sweden, in 1999. Between 2001 and 2007 he was chair profes­sor at the Center for Physical Electronics, Technical University of Denmark. From 2005 to 2014 he had a 20% position as analog/RF designer at Ericsson AB in Lund, Sweden. Since 2007, he has been associate professor at the dept. of Electrical and Information Technology (EIT), Lund University, working in analog/mixed-mode/RF IC design. He is also the head of the VINNOVA Center for System Design on Silicon, hosted by EIT. He has been a TPC member of ISSCC (2007-2012), is a TPC member of ESSCIRC (chair of the Frequency Generation subcommittee since 2012, TPC chair in 2014) and RFIC, and Associate Editor of JSSC. He has been an IEEE SSCS Distinguished Lecturer since 2017. He has authored numerous papers on harmonic oscillators and phase noise.