FPGA Compute Processing Technologies and Workflows

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A High Plains Section and Signal Processing Society Sponsored Event


Presentation Focus:   Evolution of FPGA Compute Hardware, Algorithm development and Programming Methodologies.

Abstract:

Beginning with the inclusion of simple multiplier blocks at the 130nM process node, FPGA compute hardware solutions have continually evolved becoming more capable, flexible, and scalable with each generation.   These embedded compute elements, together with high density RAM elements, flexible logic modules, and ubiquitous interconnect support implementation of extremely compute intensive algorithms in a power efficient manner.

Growing FPGA compute capabilities provide more options for implementation and more options to manage data flow and for partitioning complex compute operations between hardware and software. Algorithm Developers, Software Programmers, Embedded Programmers and FPGA Hardware Engineers can all contribute to this process and tool chains are evolving to support this collaboration. Complex systems also must be verified which drives the need for a more unified flow that supports all phases of the development process. Higher level tools have evolved to the point where there are several alternatives from which to choose.



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  • 228 East 4th Street
  • Loveland, Colorado
  • United States 80537
  • Building: Rialto Center, 2nd Floor
  • Room Number: Deveraux Room
  • Click here for Map

Staticmap?size=250x200&sensor=false&zoom=14&markers=40.3951575%2c 105
  • Co-sponsored by jlagrotta@gmail.com
  • Registration closed


  Speakers

Mark Moyer

Topic:

FPGA Compute Processing Technologies and Workflows

Presentation Focus:   Evolution of FPGA Compute Hardware, Algorithm development and Programming Methodologies.

Abstract:

Beginning with the inclusion of simple multiplier blocks at the 130nM process node, FPGA compute hardware solutions have continually evolved becoming more capable, flexible, and scalable with each generation.   These embedded compute elements, together with high density RAM elements, flexible logic modules, and ubiquitous interconnect support implementation of extremely compute intensive algorithms in a power efficient manner.

Growing FPGA compute capabilities provide more options for implementation and more options to manage data flow and for partitioning complex compute operations between hardware and software. Algorithm Developers, Software Programmers, Embedded Programmers and FPGA Hardware Engineers can all contribute to this process and tool chains are evolving to support this collaboration. Complex systems also must be verified which drives the need for a more unified flow that supports all phases of the development process. Higher level tools have evolved to the point where there are several alternatives from which to choose.

Biography:

Mark Moyer is a Field Applications Engineer with Intel Corporation providing local and remote support to worldwide Intel customers developing FPGA based designs for the Data Center, Industrial, Communications, and Test and Measurement markets.

  • Ten + years implementing analog, mixed signal and digital read/write channel and servo channel designs in data storage products.
  • Fifteen years supporting FPGA design development for Altera and now Intel.

 

B.S. Electrical Engineering, University of Colorado Denver 1992





Agenda

6:00-6:30 pm Networking Time

6:30-6:45 business Meeting

6:45 -8:30 Main Presentation