IEEE SPS, IES & CASS Joint Technical Session Hosted by IEEE VNRVJIET Student Branch|An insightful session on: Signal Processing in Electronic Product Architecture, Design and Validation

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IEEE SPS, IES Chapters Hyderabad Section in association with IES, SPS &  CASS  IEEE VNRVJIET SB|An insightful session on: Signal Processing in Electronic Product Architecture, Design and Validation|22 December 2025|2:00 PM – 3:30 PM

IEEE SPS, IES Chapters Hyderabad Section in association with IES, SPS &  CASS  IEEE VNRVJIET Student Branch
We are glad to invite you to an insightful session on: Signal Processing in Electronic Product Architecture, Design and Validation

Abstract: 
Signal processing is the core engine behind modern electronic, automotive (EV), aerospace, and defence-grade electronic systems. This session outlines the complete role of a Signal Processing Engineer—from translating system-level requirements into architectures, to implementing algorithms on DSP, FPGA, and embedded platforms. We will examine how specifications such as range, resolution, bandwidth, and interference tolerance guide choices in sampling, filtering, detection, modulation, and beamforming. The talk highlights practical workflows including simulation modelling, test-vector generation, spectral/temporal analysis, and validation using MATLAB, Python, and advanced RF/DAQ instruments. Real-world examples from EW receivers, radar front ends, EV sensor fusion, and wireless links illustrate how algorithms evolve from whiteboard concepts to production-ready implementations. Emphasis is placed on performance verification under noise, channel impairments, jamming, and environmental stress. The session also covers how engineers communicate technical insights—turning SNR, BER, and detection metrics into intuitive demonstrations for stakeholders.
The talk will also outline the knowledge and skills required for this role, specifically targeting electronic product design for the defence and aerospace industries.

🎙️ Resource Person:
Mr. K. Srinivasa Raju
CEO, Unistring Tech Solutions
Biodata
Mr. K. Srinivasa Raju is the Chief Executive Officer of Unistring Tech Solutions (UTS), a subsidiary of ZEN Technologies, where he leads advanced innovation in Electronic Warfare (EW), Radar, and Anti-Drone Systems. He holds an M.Tech from the Indian Institute of Science (IISc), Bangalore, and a B.Tech from NIT Warangal. Before joining UTS, he served as a scientist at the Defence Electronics Research Laboratory (DLRL), DRDO, from 2003 to 2014, contributing significantly to the development of cutting-edge EW systems. At UTS, he leads the company’s core R&D divisions, including system design, digital signal processing, and VLSI, while also overseeing HR and training to build a strong, industry-ready workforce. He holds two patents and has several publications in the fields of EW and radar. Mr. Srinivasa Raju is passionate about advancing technological capabilities and fostering skill development to meet the evolving needs of the defence and allied sectors.
📅 Date: 22 December 2025
⏰ Time: 2:00 PM – 3:30 PM
📍 Venue: K. S. Auditorium, VNR VJIET
✨ “Innovation begins where engineering intuition meets signal processing intelligence.”
This session will explore how advanced signal processing techniques shape modern electronic product design, architecture, and validation.
We welcome all students and faculty members to join and benefit from this expert talk.


  Date and Time

  Location

  Hosts

  Registration


  • Add_To_Calendar_icon Add Event to Calendar
  • VNR Vignana Jyothi Institute of Engineering and Technology
  • Hyderabad, Telengana
  • India 500090
  • Building: KS Auditorium
  • Contact Event Hosts

  • padmasai_y@ieee.org |anilkumar_chevella@vnrvjiet.in





Agenda

Inviting Participants 
Welcome address 

Introduction of the Speaker
Session by Mr. K. Srinivasa Raju
                  CEO, Unistring Tech Solutions

Concluding Remarks
Vote of Thanks


IEEE SPS, IES Chapters Hyderabad Section in association with IES, SPS &  CASS  IEEE VNRVJIET SB|An insightful session on: Signal Processing in Electronic Product Architecture, Design and Validation|22 December 2025|2:00 PM – 3:30 PM


  Media

REPORT_UTS_22DEC25 7.45 MiB