[Legacy Report] DL on Technology and circuit Co design for power reduction in nano scale era

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The joint chapter of IEEE Electron Devices and Circuits

and Systems societies(ED/CAS)Hyderabad Section,

organized a Distinguished lecture program by Dr. Rajiv

V. Joshi, Researcher, T.J. Watson Research Center,

IBM, USA . The lecture was held at two venues spread

over different geographical locations across the

Hyderabad City for the benefit of the IEEE student

members and host institutes.

Dr. Rajiv presented a lecture on “Technology and

circuit Co design for power reduction in nano

scale era” at Vasavi Engineering College on 23rd

January 2015 in the morning session. An audience of

about 150 participants from varied backgrounds like

industry professionals, Ph.D Scholars, postgraduate and

undergraduate students were present. Dr. Joshi

addressed on nanometer design challenges with special

focus on planar and non planar devices. He also

elaborated on impact of technology on process

variations, and reliability issues arising thereof. Finally,

he addressed on low power design techniques

employed in circuits for logic, Memory and with special

focus on SRAM. The lecture was followed by a very

interesting session of question and answers. The

audience was very keen in design aspects of Fin FETS

specially on the tri gate structure of fin FETS and their

applications.

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