Robert Clark of TEL Technology Center America

The semiconductor industry has embraced the use of Atomic Layer Deposition (ALD), a process for film deposition utilizing repeating cycles of sequential self-limited depositions, as the technology of choice for manufacturing High K gate dielectrics for leading edge transistors. The recent introduction of 22nm tri-gate transistors by Intel emphasizes the need for additional ALD-like processes, including for metal gates, spacers for sidewall image transfer and for etch stop layers. The majority of leading edge logic manufacturing is expected to follow a similar path and introduce FinFETs for production at 14nm technology nodes. Advanced memory production is also reliant on ALD/Molecular Layer Deposition (MLD) high K dielectrics for use as the DRAM capacitor dielectric. However, the potential of atomic level control, exemplified by ALD, is far from being fully realized. The use of anneals and other treatments interspersed during the ALD process has recently been shown to provide several opportunities for film optimization. With appropriate material choices we are able to reduce impurities and defects in the resulting films as well as create texturing and select the crystal phase of the film using interspersed treatments or anneals. Forming nano-laminates, controlled compositional gradients, and designed superlattices can also be enabled by ALD-like processes. New applications for ALD and related processes are currently under investigation including the use of ALD for doping in addition to a related process known as mono-layer doping. The use of ALD layers for regulating the Schottky barrier height at metal/semiconductor interfaces was recently demonstrated as well. Related to ALD in principal, self-limited etching and oxidation processes provide the potential for feature thinning, as well as more tightly controlling interface layers between films- leading to designed interfaces. As scaling continues, the so-called “explosion of ALD” and related processes will continue to escalate in order to provide new materials, tighter control in 3 dimensions, and ultimately better performance. Beyond traditional CMOS and DRAM scaling as new devices are incorporated and scaled in future nano-systems, ALD and related processes will become dominant process technologies enabling the continuing growth of functionality, and thus continuing to enable the next node, the next device, and the next system even beyond the foreseeable roadmap. The above examples of technologies currently in use or under investigation will be described and discussed to illustrate the potential for ALD and related processes in the future. Finally, the potential of ALD-like processes to enable future devices and structures leads to the conclusion that there is still plenty of room at the bottom.

Biography: Robert D. Clark holds B.S. and M.S. degrees in chemistry from Virginia Polytechnic Institute and State University, earned in 1993 and 1995 respectively. In 2000 he completed his Ph.D. in Chemistry at the University of California, Irvine under the direction of Professor William J. Evans. Following his education he began his career working for the Schumacher unit of Air Products and Chemicals where he served as the technical lead for High K and metal gate precursor development. During his time at Schumacher/Air Products he successfully developed the first precursor used in high volume manufacturing for ALD High K gate dielectric deposition, and was co-inventor of the patented solid source container used for its vapor delivery. In 2006 he joined Tokyo Electron (TEL) at the TEL Technology Center, America LLC located in Albany, NY where he worked on new process development, primarily for ALD High K dielectrics and Vt adjustment layers. In 2010 he was elected Member of the Technical Staff for TEL U.S. and relocated to the Silicon Valley, where he currently works and resides. His current research focus is on unit process development incorporating ALD dielectric and metal layers for use in advanced logic and memory devices. He is a member of the Wafer and Environmental Contamination Control committee of the ITRS where he provides expertise related to FEOL precursors for ALD and CVD. He is also an active liaison and participant in SRC Device Sciences where he serves on the Technical Advisory Boards for Digital CMOS and Memory Technologies, as well as serving as the Vice Chair of the Device Sciences Science Area Coordinating Committee. He currently holds 23 issued U.S. Patents and has authored/co-authored more than 60 publications and conference presentations.

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Address:TEL Technology Center America, 3100 West Warren Ave., Fremont, California, United States, 94538

Robert Clark of TEL Technology Center America

Biography:

Email:

Address:Fremont, California, United States