Karan Bhatia, "Overcoming CMOS Imperfections for Successful Analog/RF Design in SoCs"
Advanced System-on-Chips (SoCs) require that analog, RF, and digital subsystems co-exist on the same piece of silicon. The process technologies used to build these SoCs are tailored to maximize digital circuit performance at the expense of analog/RF performance. In this talk, we will review the analog/RF performance metrics for transistors and passives built in these advanced CMOS processes. This will be followed by design examples and discussions of common challenges and solutions needed to overcome the analog/RF performance limitations of the chosen SoC process technology.
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- University of Texas at Dallas
- Dallas, Texas
- United States
- Building: EE & CS
- Room Number: 3.503, Osborne
Speakers
Karan Bhatia of Texas Instruments, Inc.
Biography:
Karan Bhatia is Member Group Technical Staff at Texas Instruments, Inc. in Dallas, TX where his main duties involve RF/analog/mixed-signal circuit design and testing. He also has a strong knowledge of ESD and other reliability issues in advanced CMOS processes. Karan Bhatia received the B.S.E.E. degree from the University of Texas at Austin in 2002 and an M.S.E.E. degree from the University of Illinois at Urbana-Champaign (UIUC) in 2006. He completed the Ph.D. degree in electrical engineering at UIUC in August 2008. Karan holds 4 US patents and has authored/co-authored 9 publications in IEEE-sponsored conferences and journals. He is an Organizing and Steering Committee member for the IEEE International System-on-Chip Conference and served as its Technical Program Chair for the 2016 conference. He also is a member of the Technical Program Committee for the International Symposium on Quality Electronic Design and a Senior Member of the IEEE.
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