Synopsys Seminar (Madrid)
This event is a one-day technical seminar providing a complete overview of Synopsys Analog custom design and verification Platform. Synopsys Custom Compiler is a modern Analog Design environment allowing you to drastically reduce your schematic and layout effort.
In this session we will demonstrate how Custom Compiler's visually-assisted automation has transformed analog layout methodology, and show you how Custom Compiler's assisted placement, assisted routing, and template-based design reuse capabilities can reduce layout tasks from days to hours. The seminar will also highlight the tight integration with Synopsys Analog Mixed Signal verification tools (HSpice, FineSim and CustomSim) Synopsys physical verification and parasitic extraction (IC Validator & StarRC) to deliver a “Custom IC design Platform”. A testimonial will also be provided by IMASENIC Advanced Imaging.
Who Should Attend: Engineers and managers who are interested in Analog and Custom Design.
Date and Time
- Date: 29 January 2018
- Time: 10:00 AM to 05:00 PM
- All times are Europe/Madrid
- Add to Google Calendar
- Universidad Complutense de Madrid
- Calle del Prof. José G. Santesmases 9
- Madrid, Madrid
- Spain 28040
- Building: Facultad de Informatica
- Co-sponsored by STB61991 - Universidad Complutense de Madrid
10:00 a.m. Introduction
10:15 a.m. Synopsys Analog Custom IC flow overview
10:45 a.m. Custom Compiler Schematic Edition, Simulation Environment demo
1:00 p.m. Lunch (provided)
2:00 p.m. Layout Edition, in-design verification & parasitic extraction
3:30 p.m. Break
4:00 p.m. Testimonial and Q&A
5:00 p.m. Finish