[Legacy Report] IEEE seminar by Vaibhav Tripathi on "Analog to Digital Converters in Nano-CMOS Technologies"

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Over the past few decades, electronic devices have pervaded all walks of our life.
These complicated systems use a variety of semiconductor circuits to realize the
end-user experience. One such circuit block is the ‘Analog to Digital Converter
(ADC)’ that is present in almost all modern day devices: from washing machines to
wireless routers, from hard disk drives to cell phones and base stations. As we move
towards a time of increasingly more sensors around us (e.g. iPhone), ADC’s get ever
more important as the real world remains ‘Analog’ while the digital signal
processing becomes cheaper with CMOS scaling.

This research focuses on ‘Successive Approximation Register (SAR)’ A/D converter
architecture, which has seen significant improvement in performance especially over
the past 5 years. A SAR ADC employs sequential binary search algorithm to convert
analog input into digital bits. Using only a comparator, capacitors and digital
logic, it is known for excellent power efficiency and scaling characteristics. The
first part of this work presents a study of mismatch statistics of very small (~ <
1fF) on chip metal-oxide-metal (MOM) capacitors, which are routinely used as unit
caps
in state-of-the-art SAR ADCs. The second part explores speed limits of a
conventional SAR architecture and aims at pushing its conversion speed resulting in
the design of an 8 bit, 450 MS/s SAR A/D converter in 65nm CMOS process. Finally,
the design of a 68.3 dB SNDR, 160 MS/s SAR ADC will be presented that employs a
pipelined SAR ADC architecture with two capacitive DACs in the frontend.
Measurement results confirm the proposed design and confirm that this is a viable
approach of integrating such ADCs with the digital backend in aggressively scaled
CMOS processes.

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