[Legacy Report] Timing Closure at Advanced Nodes

#VLSI #Design #STA #Delay #Estimation #variation #advanced #nodes
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This talk describes some of the challenges in timing closure at advanced nodes. The first half of the presentation gives an overview of static timing analysis (STA), what are corners, what are parasitics, and what kind of checks are checked in STA. The presentation also provides a brief explanation of how interconnect delay is computed, and what are late and early paths.

The second half of the talk focuses on some of the issues pertaining to advanced nodes, namely variation, inversion and run time complexity. Variation can be local and global. Inversion can cause non-intuitive corners to have worse times. And run time complexity is getting everyone worried about the cost of doing STA.


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  • Newark, New Jersey
  • United States

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  • Co-sponsored by MTT/AP-S & ED/CAS


  Speakers

Jayaram Bhasker of eSilicon Corporation

Topic:

Timing Closure at Advanced Nodes

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Address:Allentown, Pennsylvania, United States