Challenges and Opportunities for Efficient & Scalable Neuromorphic Systems
Electrical & Computer Engineering Colloquium Talk
The emerging Internet of Everything (IoE) era will demand cyberphysical systems that continuously interact with the physical sensory world and are capable of information processing, learning, cognition, inference and automated action, much like the living “brain-body-environment” interactive systems in nature. These cyberphysical systems need to be extremely energy efficient, scalable in size from mm-scale at the edge of IoE to km-scale in the backend cloud datacenters, and universal in their capabilities to support a variety of existing and emerging functions seamlessly. The fundamental neurosynaptic architecture of the brain demonstrates such phenomenal efficiency and scalability in nature. We will discuss the challenges and opportunities for building neuromorphic systems that emulate some of the useful functional mechanisms of the brain by utilizing Moore’s Law scaling, and CMOS as well as beyond-CMOS technologies. Going well beyond evolutionary Von Neumann computing and machine learning, the neuromorphic computing systems of the future will feature efficient & sparse spatio-temporal information encoding, fully distributed memory & compute, scalable “small world” networks, structural & synaptic plasticity, asynchronous & event-driven operation, continuous & distributed learning, autonomous power management including homeostasis, stochasticity, adaptivity, variation tolerance & resilience.
Date and Time
Location
Hosts
Registration
- Date: 09 Mar 2018
- Time: 10:30 AM to 11:59 AM
- All times are (GMT-08:00) Canada/Pacific
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- Electrical & Computer Engineering
- 2332 Main Mall
- Vancouver, British Columbia
- Canada V6T1Z4
- Building: Kaiser
- Room Number: 2020
- Contact Event Host
- Co-sponsored by Sudip Shekhar
- Starts 24 February 2018 08:14 PM
- Ends 09 March 2018 10:15 AM
- All times are (GMT-08:00) Canada/Pacific
- No Admission Charge
Speakers
Vivek De of Intel Corporation
Biography:
Vivek De is an Intel Fellow and Director of Circuit Technology Research in Intel Labs. He is responsible for providing strategic technical directions for long term research in future circuit technologies and leading energy efficiency research across the hardware stack. He has 267 publications in refereed international conferences and journals with a citation H-index of 68, and 219 patents issued with 31 more patents filed (pending). He received an Intel Achievement Award for his contributions to an integrated voltage regulator technology. He received a Best Paper Award at the 1996 IEEE International ASIC Conference, and nominations for Best Paper Awards at the 2007 IEEE/ACM Design Automation Conference (DAC) and 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). He also co-authored a paper nominated for the Best Student Paper Award at the 2017 IEEE International Electron Devices Meeting (IEDM). One of his publications was recognized in the 2013 IEEE/ACM Design Automation Conference (DAC) as one of the "Top 10 Cited Papers in 50 Years of DAC". Another one of his publications received the “Most Frequently Cited Paper Award” in the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017. He was recognized as a Prolific Contributor to the IEEE International Solid-State Circuits Conference (ISSCC) at its 60th Anniversary in 2013, and a Top 10 Contributor to the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017 . He served as an IEEE/EDS Distinguished Lecturer in 2011 and an IEEE/SSCS Distinguished Lecturer in 2017-18. He received the 2017 Distinguished Alumnus Award from the Indian Institute of Technology (IIT) Madras. He received a B.Tech from IIT Madras, India, a MS from Duke University, Durham, North Carolina, and a PhD from Rensselaer Polytechnic Institute, Troy, New York, all in Electrical Engineering. He is a Fellow of the IEEE.