A Scalable, High-density ECoG Recording Architecture for Bi-directional Brain Computer Interfaces
Bi-directional Brain Computer Interfaces (BBCI), systems capable of recording from, and providing stimulus to the nervous system offer great promise for helping patients with motor defects, and serve as a critical tool for the understanding of the Brain. It is anticipated that future BBCI systems will require processing over a thousand channels between stimulus and recording, while maintaining power, volume, and precision constraints.
Much progress has been made in recent years to advance the state-of-the-art in integration and power dissipation. However, existing methods, largely extensions of traditional approaches to Analog-Front-End (AFE) design do not scale well to the new thousand channel paradigm. Further, the problem of canceling artifacts of stimulation during recording are challenges-Significant improvement is required in differential artifact cancellation, and common mode cancellation remains an open problem.
In this talk, I will discuss recent work in my group focusing on circuit-architectures that address two key areas (1) scalability in frequency, channel-count and process-technology (2) Exploiting the signal statistics of neural signals to meet challenging system level performance ~(e.g. 14b ADC resolution) using much simpler, robust, low-power circuits. Silicon measurements of a 64-channel prototype in 65nm CMOS will be discussed.
http://www.ece.utexas.edu/events/scalable-high-density-ecog-recording-architecture-bi-directional-brain-computer-interfaces
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- Date: 18 Apr 2018
- Time: 12:00 PM to 01:00 PM
- All times are (UTC-05:00) Central Time (US & Canada)
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- Starts 10 April 2018 12:18 AM
- Ends 18 April 2018 12:00 PM
- All times are (UTC-05:00) Central Time (US & Canada)
- No Admission Charge
Speakers
Visvesh S. Sathe
A Scalable, High-density ECoG Recording Architecture for Bi-directional Brain Computer Interfaces
Biography:
Visvesh S. Sathe joined the University of Washington Department of Electrical Engineering in 2013. Prior to joining the faculty at the University of Washington, he served as a Member of Technical Staff in the Low-Power Advanced
Development Group at AMD, where his research focused on inventing and developing new technologies for next-generation microprocessors. Dr. Sathe has led the research and development effort at AMD that resulted in the first-ever
resonant clocked commercial microprocessor. Several of his inventions in the area of high performance digital circuits and adaptive clocking for supply noise mitigation have been incorporated into current and next generation microprocessors. His research interests lie at the intersection of digital and mixed-signal circuits and architectures for energy efficient computing and bio-medical electronics.