Workshop on VLSI Current Trends Using Mentor Graphics & Xilinx

#Xilinx #Vivado #VLSI #VHDL
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Department of Electronic Science, University of Delhi South Campus in collaboration with  IEEE Electron Devices Society Delhi Chapter and CoreEL technologies organized a Workshop on VLSI Current Trends Using Mentor Graphics & Xilinx on 21-22 March, 2018. In this workshop the resource persons first discussed the basics of Xilinx seven series FPGA Architecture. Hands on training was then done on Xilinx Vivado software along with hardware implementation. Various features of Vivado Tool such as synthesis of a RTL design, static timing analysis, I/O port mapping, Xilinx Design Constraints etc. were explained and utilized in various hands on sessions.


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  • Start time: 21 Mar 2018 12:00 AM UTC
  • End time: 22 Mar 2018 08:00 AM UTC
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  • Department of Electronic Science
  • University of Delhi South Campus
  • Delhi, Delhi
  • India
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  Speakers

Ankur Sangal of CoreEL technologies

Topic:

VLSI Current Trends Using Mentor Graphics & Xilinx

Biography:

Mr. Ankur Sangal received the B. Sc and M. Sc degree in Electronics from Kurukshetra University, Haryana, and Bundelkhand University, Jhansi, India, in 2005 and 2007 respectively. He received the M. Tech degree in VLSI Design from CDAC NOIDA, GGSIP University, Delhi in 2009. He has more than 9 years of experience in VLSI design. He is currently working as a senior application engineer with CoreEL Technologies.