3D Integrated Circuit Technology
3D Technology refers to a family of techniques and methods which enable the stacking of active Si layers with vertical connections between them. 3D stacking has the ability to enhance chip performance by increasing bandwidth, reducing wire delay, and enabling better power management. While there are different approaches to achieving 3D integration, a key element of all 3D methods is the TSV (Through Silicon Via). TSV fabrication, insulation, metallization, and integration into the BEOL (Back End Of Line) are key considerations in 3D stacking, along with the thermo-mechanical integrity and reliability of TSV structures. Additionally, one must also consider the impact of TSVs on devices. Several researchers have studied these aspects of 3D technology. This talk begins with an understanding of the prime drivers for 3D stacking. We will then review some of the published work in order to better understand the various options and schemes in 3D technology. Before concluding, we will take a look at the key challenges that must be overcome before successful introduction of this technology into semiconductor manufacturing.
Date and Time
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- 161 Warren St
- Newark, New Jersey
- United States 07102
- Building: ECE Building, Room 202
- Click here for Map
- Contact Event Host
- Durga Misra (973) 596-5739 (dmisra “AT†njit.edu) or Dr. Edip Niver (973) 596-3542 (NJIT)
- Co-sponsored by ECE Dept, NJIT
Speakers
Mukta Farooq of Semiconductor R&D Center, IBM Systems & Technology Group
3D Integrated Circuit Technology
3D Technology refers to a family of techniques and methods which enable the stacking of active Si layers with vertical connections between them. 3D stacking has the ability to enhance chip performance by increasing bandwidth, reducing wire delay, and enabling better power management. While there are different approaches to achieving 3D integration, a key element of all 3D methods is the TSV (Through Silicon Via). TSV fabrication, insulation, metallization, and integration into the BEOL (Back End Of Line) are key considerations in 3D stacking, along with the thermo-mechanical integrity and reliability of TSV structures. Additionally, one must also consider the impact of TSVs on devices. Several researchers have studied these aspects of 3D technology. This talk begins with an understanding of the prime drivers for 3D stacking. We will then review some of the published work in order to better understand the various options and schemes in 3D technology. Before concluding, we will take a look at the key challenges that must be overcome before successful introduction of this technology into semiconductor manufacturing.
Biography:
Dr. Mukta Farooq is a Senior Technical Staff Member & Master Inventor at IBM’s
Semiconductor R&D Center. She is also currently the Chief Technologist for 3-
Dimensional Chip Development at IBM Microelectronics.
Mukta has over 24 years of professional experience as a materials scientist at
IBM. Her areas of expertise include semiconductor materials and structures,
CMOS FET (Complementary Metal Oxide Semiconductor - Field Effect
Transistor) structures & processes, 3-Dimensional silicon integration, flip-chip
technology, lead-free alloys, chip package interaction, and intellectual property
development. She has over 123 issued US & international patents, including
several which have been designated as high value because of their use in
semiconductor manufacturing. Mukta has also authored 23 external publications
and given invited talks at various technical symposia. She is the Chair of the site
wide IBM Master Inventor Committee which is charged with appointing new
Master Inventors.
Mukta is a Senior Member of IEEE (Institute of Electrical and Electronics
Engineers), and holds the position of Distinguished Lecturer of the IEEE Electron
Devices Society. She is also currently the Chair of the IEEE Mid Hudson Valley
EDS Chapter.
Mukta is passionate about mentoring professionals in engineering & technology
disciplines. Mukta has also been active in mentoring middle-school children to
pursue science and math.
Mukta holds a Ph.D. in Materials Science & Engineering from Rensselaer
Polytechnic Institute, an M.S. in Materials Science from Northwestern University,
and a B. Tech. in Metallurgical Engineering from the Indian Institute of
Technology, Bombay.
Email:
Address:Semiconductor R&D Center, IBM Systems & Technology Group, 2070 Route 52 , Hopewell Junction, New York, United States, 12533
Mukta Farooq of Semiconductor R&D Center, IBM Systems & Technology Group
3D Integrated Circuit Technology
Biography:
Email:
Address:Hopewell Junction, New York, United States
Agenda
Talk at 5 pm
ECE Building Room 202, NJIT
You do not have to be a member of the IEEE to attend.