IEEE-EDS Lecture by Dr. Tushar Sharma on "Modelling and Design Methodology of High Efficiency Harmonic Tuned Power Amplifiers for 5G Applications" (Wed, 23rd May)
Critical to the enablement and the fulfillment of next generation network energy efficiency, Power amplifiers (PAs) remain a center of focus to RF power base station markets. With an immense increase in cellular traffic, the performance of PAs should be constantly improved in terms of power efficiency, linearity, and bandwidth. The talk focuses on several aspects for enabling high efficiency and bandwidth for small cell PAs for 5G applications. A variety of PA design methodologies for broadband class F, F-1,2nd HT have been proposed and implemented to achieve state of the art performance. The talk focuses of different aspects of RF Power transistors technology evaluation specific to gallium-nitride based PAs. For the first time, class GF and GF-1 amplifiers which have demonstrated outstanding performance by simultaneously tackling both input and output harmonics have been demonstrated. The talk also addresses the conventional mystery of so called second harmonic efficiency “null” in design of high efficiency PAs. The study reveals new directions for active harmonic load pull and design procedure for high efficiency PAs, which enables PAs in context of wide bandwidth, high efficiency without compromising the quality of service.
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- IIT Kanpur
- EE
- Kanpur, Uttar Pradesh
- India 208016
- Building: ACES
- Room Number: DA229
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- Co-sponsored by IEEE EDS-UP Chapter (ED15)
- Starts 01 May 2018 12:52 PM UTC
- Ends 23 May 2018 12:52 PM UTC
- No Admission Charge
Speakers
Tushar Sharma
Internet of things (IoT) has become a rapidly emerging application space with potential to become the largest electronics market for semiconductor industry. Because of diversity, IoT application space is characterized by two design constraints: low power consumption/power management and low cost are the major design concerns. The central idea for low power high performance design is to use high threshold voltage (VT) transistors to reduce leakage current and low threshold voltage transistors to achieve high performance. Threshold voltage variability due to process technology variations is an inherent feature in semiconductor devices. The intrinsic sources of variability in CMOS circuit performances arise from random-variability of the manufacturing process steps. Lower VT variability (σVT) reduces number of leaky low VT devices. Power dissipation is dominated by low VT edge of distribution. This talk discusses in a comprehensive manner, the sources of process variability, the strategies to incorporate the effects of process variability in circuit simulation. Finally, the talk introduces a new type of planar MOSFET structure which is targeted towards low cost applications. Epitaxial delta doped channel (EδDC) MOS transistor, based on planar MOS technology reduces the threshold voltage variability due to random discrete dopant (RDD) effect through vertical channel engineering. The basic idea of drain current mismatch due to RDD is introduced and ways to reduce the effects of drain current mismatch is discussed in a comprehensive manner.
Biography:
Tushar Sharma (S’10) received the B.Tech. Degree in electronics and communications engineering from Guru Gobind Singh Indraprastha University, Delhi, India. He completed Ph.D. degree at the University of Calgary, Calgary, AB, Canada in 2018. In 2016 and 2017, he joined NXP Semiconductors, Chandler, AZ, USA, as a Research and Development RF engineer to work in field of gallium nitride technology evaluation and design for 5G base station. Mr. Sharma is a recipient of the Izaak Walton Killam Pre-Doctoral Scholarship, Alberta Science and Innovation Under 30 Future leader award ,the AITF Doctoral Scholarship, the Alberta Transformative Talent scholarship, the Academic Excellence Award, and the Research Productivity Award. He has authored and coauthored over 17 refereed publications. His current research interests include high-efficiency broadband RF power amplifiers, waveform engineering techniques for power amplifiers, and active/passive load-pull techniques.