Bonding with your Semiconductor: Understanding Ultrasonic Welding

#Semiconductor #wire #bonding #ultrasonic
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With more than 15 trillion wire bonds produced annually and volume still growing the reliability and productivity of wire bonding makes it the dominant chip interconnection method. Estimated wire bond interconnection volume exceeds 90% of market share. But that does not mean that rigorous attention to details can be ignored. New products must be fully qualified and periodic testing of the weld intermetallic is an important part of assuring high quality bonds. Process changes, materials changes and tool changes must all be tested and reliability confirmed. Long-term aging studies using accelerated high temperature storage, thermal cycling and temperature/humidity tests are not only initial qualification requirements but should be a part of any review when materials s and encapsulation changes are required.

                  Wire bonding is a welding process where an intermetallic weld nugget (an alloy of the wire and the bond pad or substrate surface) is formed by the deformation of the ball or wire (wedge bonding). Ultrasonic energy unlocks easy slip mechanisms within the crystal lattice of the deforming materials allowing deformation at lower force and temperature than the materials would otherwise require for deformation. Deformation mixes the wire and substrate to form the initial bond. Subsequently diffusion allows the mixture to resolve into the equilibrium compounds of the phase diagram. The intermetallic compounds each have different physical properties and behavior. During the life of a wire bond it is normal for transformations to occur, where one intermetallic transforms to another because diffusion has increased (or decreased) the concentration of one of the elements. Transformations can generate large strains in the lattice structure, even resulting in bond failures at the interface between adjacent intermetallic compounds.

                  This talk will discuss the ultrasonic welding mechanism and its effect on wire bond reliability

1 PDH is available for IEEE members, but you must register and sign in at the meeting.  Please indicate these when you register.



  Date and Time

  Location

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  Registration



  • Date: 25 Sep 2018
  • Time: 10:00 PM UTC to 12:00 AM UTC
  • Add_To_Calendar_icon Add Event to Calendar
  • 1 West Packer Avenue
  • Lehigh University
  • Bethlehem, Pennsylvania
  • United States 18015
  • Building: STEPS
  • Room Number: 102

  • Contact Event Host
  • Starts 06 August 2018 09:49 PM UTC
  • Ends 25 September 2018 07:00 PM UTC
  • No Admission Charge


  Speakers

Lee Levine Lee Levine

Biography:

Lee is a consultant for Process Solutions Consulting, Inc. where he provides process engineering consultation, SEM/EDS analysis, and wire bond training. Lee’s previous experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. He has been awarded 4 patents, published more than 70 technical papers, and has won both the John A. Wagnon Technical Achievement award and the Daniel C. Hughes award from the International Microelectronics and Packaging Society (IMAPs). Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding semiconductor assembly processes. He is an IMAPs Fellow and a senior, life member of IEEE.

Lee is a graduate of Lehigh University, Bethlehem, Pa where he earned a degree in Metallurgy and Materials Engineering.





Agenda

6PM - Meet & greet our speaker with refreshments.

7PM Presentation