Guest Lecture on “Shaping Up Career in VLSI Design”

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Target Audience: IV year B.Tech ECE students and Faculty

 

A guest lecture titled “Shaping Up Career in VLSI Design” organized on 23rd of
July by Entrepreneurship Development Cell in association with the ECE Dept and
IEEE student Branch, AITS, Rajampet. Mr. Avinash Yadlapti, Senior Director ,
Mirafre Technologies, Hyderabad.


  Date and Time

  Location

  Hosts

  Registration


  • Date: 23 Jul 2018
  • Time: 05:45 AM UTC to 12:54 PM UTC
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  • AITS, New Boyanapalli,
  • Rajampet
  • Rajampet, Andhra Pradesh
  • India 516126
  • Contact Event Host
  • Co-sponsored by IEEE Young Professionals Hyderabad

  Speakers

Avinash Yadlapti of Mirafra Technologies, Hyderabad

Topic:

Shaping Up Career in VLSI Design

Biography:

I am Avinash Yadlapati, with 15 years of experience in ASIC Design, Verification and Implementation (Synthesis & Timing Closure). I have worked extensively on Industry standard tools like Synopsys VCS, VCSMX, Cadence NCSIM, Mentor Tools, Synopsys Design Compiler, Synopsys Prime Time and IBM Einstimer. I have 10 years experience in the ASIC Front End activities like RTL Coding, Verification, Synthesis and LEC and close to 4 years experience in Static Timing Analysis primarily on IBM Tools and Methodologies. Completed my M.Tech (VLSI) From KL University, Vijayawada, AP and have also been trained initially at Bit Mapper Integration Technologies, Pune in ASIC Front End Methodologies. Have varied experience working at different customer sites in US, Europe, Korea, China and Singapore. I have also been instrumental in building teams and managing teams in different locations.

Address:Mirafra Technologies, , Hyderabad, Andhra Pradesh, India