Saket Srivastava

The advent of nanocomputing using emerging technologies has enabled an increase in the computational capability by continually increasing the device density. Moreover, circuits built using emerging technologies have an additional advantage of lower power dissipation as compared to CMOS technology. Due to lack of advanced fabrication facilities for emerging nanotechnologies, their adaptation on an industrial scale is unlikely in the near future. Recently, hybrid nano/CMOS architectures have been proposed that show promise in bridging the gap between CMOS and emerging nanotechnologies. Advanced fabrication techniques used in current generation CMOS technology keep defect rate below 0.05%. However, in fabrication of emerging nanotechnologies it is common to have defect rates exceeding 10%, hence incorporating defect/fault tolerance is necessary. Hybrid nano/CMOS architecture aims to utilize reliable CMOS components for providing interfacing and defect/fault tolerance while unreliable but highly dense nano systems are utilized for data storage and computation. The focus of this seminar is to discuss defect/fault tolerant techniques for hybrid nano/CMOS computational architecture that enable highly reliable computation even under high defect rates (upto 20%).

Biography: Saket Srivastava received the B.E. in electrical and
electronics engineering from the National Institute of Technology - Trichy
in 2003, and Ph.D. in electrical engineering from the University of South
Florida in 2008. Since 2008, he has been a postdoctoral research fellow in
the School of Electronics and Computer Science at University of
Southampton, U.K. He serves on the technical program committee for ISVLSI
and DATE and is a reviewer for leading international journals and
conferences. His current research interests include probabilistic modeling
of emerging nanotech devices, CAD tools for nanosystem design, and
reliability in hybrid nano/CMOS architecture.

Saket Srivastava

Biography: