Reliability of Metal Gate / High-K CMOS devices

Share

“IEEE Electron Device Society Distinguished Lecture Program”


Aggressively scaled transistor technologies with metal gate/high-k stacks encounter additional reliability challenges beside bias temperature instability (BTI) in PMOS and NMOS devices, time dependent dielectric breakdown and hot carrier degradation. Time-zero variability and variability induced by device aging is a growing concern which needs to be modeled using stochastic processes. The physical nature of the stochastic process remains under debate and to support model development efforts large statistical data sets are essential. In addition, self-heating during reliability testing can be observed in novel device structures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices and needs proper attention. Furthermore, to increase the confidence in the discrete device reliability models, device-to-circuit correlations need to be established. In this presentation we discuss how to obtain stochastic BTI data for discrete SRAM and logic device beyond 3, address device-to-circuit correlations using ring-oscillators and explore self-heating effects in FinFET and SOI devices.



  Date and Time

  Location

  Contact

  Registration



  • 154 Summit Street, Newark, NJ 07102
  • Newark, New Jersey
  • United States 07102
  • Building: ECEC
  • Room Number: 202
  • Click here for Map

Staticmap?size=250x200&sensor=false&zoom=14&markers=40.74378565%2c 74
  • Ajay K. Poddar, Ph.: 201-560-3806, email:akpoddar@ieee.org

    Durga Misra, +1-973-596-5739, email: dmisra@ieee.org

    Edip Niver, email: edip.niver@njit.edu

    Anisha Apte, email: anisha_apte@ieee.org

  • Co-sponsored by ED/CAS, AP/MTT17
  • Starts 11 August 2019 05:07 AM
  • Ends 13 September 2019 10:00 AM
  • All times are America/New_York
  • No Admission Charge
  • Register


  Speakers

Dr. Andreas Kerber
Dr. Andreas Kerber of Skorpios Technologies, Inc.

Topic:

Reliability of Metal Gate / High-K CMOS devices

Aggressively scaled transistor technologies with metal gate/high-k stacks encounter additional reliability challenges beside bias temperature instability (BTI) in PMOS and NMOS devices, time dependent dielectric breakdown and hot carrier degradation. Time-zero variability and variability induced by device aging is a growing concern which needs to be modeled using stochastic processes. The physical nature of the stochastic process remains under debate and to support model development efforts large statistical data sets are essential. In addition, self-heating during reliability testing can be observed in novel device structures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices and needs proper attention. Furthermore, to increase the confidence in the discrete device reliability models, device-to-circuit correlations need to be established. In this presentation we discuss how to obtain stochastic BTI data for discrete SRAM and logic device beyond 3, address device-to-circuit correlations using ring-oscillators and explore self-heating effects in FinFET and SOI devices.

Biography:

Andreas Kerber received his Diploma in physics from the University of Innsbruck, Austria, in 2001, and a PhD in electrical engineering from the TU-Darmstadt, Germany, with honors in 2014. From 1999 to 2000 he was an intern at Bell Laboratories, Lucent Technologies (Murray Hill, NJ, USA) working on the electrical characterization of ultra-thin gate oxides. From 2001 to 2003, he was the Infineon Technologies assignee to International SEMATECH at IMEC in Leuven, Belgium, where he was involved in the electrical characterization of alternative gate dielectrics for sub-100 nm CMOS technologies. From 2004 to 2006, he was with the Reliability Methodology Department at Infineon Technologies in Munich, Germany, responsible for the dielectric reliability qualification of process technology transfers of 110 and 90 nm memory products. During that time he developed a low-cost, fast wafer-level data acquisition setup for time-dependent dielectric breakdown (TDDB) testing with sub-ms time resolution. From 2006 to 2018 he was working for AMD in Yorktown Heights, NY, and GLOBALFOUNDRIES in Malta and East-Fishkill, NY, as a Principal Member of Technical Staff on front-end-of-line (FEOL) reliability research with focus on metal gate / high-k CMOS process technology, advanced transistor architecture and device-to-circuit reliability correlation. In 2018 he joined Skorpios Technologies in Albuquerque, NM, working on reliability of Si-photonic devices and currently he is exploring new opportunities in the semiconductor industry.
Dr. Kerber has contributed to more than 100 journal and conference publications and presented his work at international conferences, including the IEDM, VLSI and IRPS. In addition, he has presented tutorials on metal gate / high-k reliability characterization at the IIRW, IRPS and ICMTS. Dr. Kerber has served as a technical program committee member for the SISC, IRPS, IEDM, Infos, ESSDERC, is a Senior Member of the IEEE and a Distinguished Lecturer (DL) for the IEEE Electron Devices Society.

Email:

Address:Skorpios Technologies, Inc., , Albuquerque, New Mexico, United States, 87109





Agenda

11:00 AM - Refreshments and Networking

11:15AM-12:15 PM: Talk by Dr. Andreas Kerber, Senior Principal Engineer at Skorpios Technologies, Inc., USA

You do not have to be an IEEE Member to attend. Refreshmen is free for all attendess. Please invite your friends and colleagues to take advantages of this Invited Distinguished Lecture.



Co-sponsor by ED/CAS and MTT/AP Chapters