Interface Physics, Reliability and Analysis Challenges in Si Nanodevices

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As the dimensions shrink, one of the major challenges in device technology is controlling various parameters to obtain high reliability.  Studies on interfaces of basic transistor structure have shown un-assumable problems through physical analysis which provide insights into the device reliability. Physical analysis studies on device gate structures involving ultra-thin gate dielectrics and related interfaces are discussed. These studies provide deep insight into the device physics in terms of electron conduction through interfaces which in turn reveals certain challenges in the technology progression. An overview of such studies to understand the conduction mechanisms, microstructural damages, interface interactions as well as the physical effects in the structural integrity is discussed in this talk.



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  • 154 Summit Street, Newark, NJ 07102
  • Newark, New Jersey
  • United States 07102
  • Building: ECEC
  • Room Number: 202
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  • Contact Event Host
  • Ajay K. Poddar, Ph.: 201-560-3806, email:akpoddar@ieee.org

    Durga Misra, +1-973-596-5739, email: dmisra@ieee.org

    Edip Niver, email: edip.niver@njit.edu

    Anisha Apte, email: anisha_apte@ieee.org

  • Co-sponsored by AP/MTT17, ED/CAS
  • Starts 01 November 2019 02:00 PM UTC
  • Ends 04 December 2019 05:00 AM UTC
  • No Admission Charge


  Speakers

Dr. M. K. RADHAKRISHANAN Dr. M. K. RADHAKRISHANAN

Topic:

Interface Physics, Reliability and Analysis Challenges in Si Nanodevices

As the dimensions shrink, one of the major challenges in device technology is controlling various parameters to obtain high reliability. Device reliability is the resultant of various analyses of the design, process and product and understanding innumerable phenomenon to control the extension of even atomic level defects, especially when the dimensions are at nanometer level. Understanding the physical phenomenon with which devices mal-function becomes more striving in solving both the device and process problems. Difficulties arise in the area of fault localization, physical failure analysis as well as identifying the physical phenomenon and solving the related problems. One of the most important and challenging area is interfaces and comprehending the related issues. Studies on interfaces of basic transistor structure have shown un-assumable problems through physical analysis which provide insights into the device reliability. Physical analysis studies on device gate structures involving ultra-thin gate dielectrics and related interfaces are discussed. These studies provide deep insight into the device physics in terms of electron conduction through interfaces which in turn reveals certain challenges in the technology progression. An overview of such studies to understand the conduction mechanisms, microstructural damages, interface interactions as well as the physical effects in the structural integrity in will be discussed in this talk.

Biography:

Dr. M.K. Radhakrishnan (M82, SM94, LSM18) is the Founder Director of NanoRel LLP -Technical Consultants Singapore providing analysis-based solutions to micro and nano electronic industries for improving design and process reliability of devices. As a researcher in the area of semiconductor devices, analysis and reliability physics for more than 40 years, he worked as a Senior Member Technical Staff with the Institute of Microelectronics Singapore (1993-2001), Director and Principal Consultant to Philips Electronics Singapore/Netherlands (2001-2004), Device Program Leader in ST Microelectronics (1991-1993) and a Scientist in ISRO (1985-1991). He was an Adjunct Professor at National University of Singapore (1994-2007). Radhakrishnan was a Senior Consultant to ITU, Geneva as a UN Expert in the area of Reliability and Failure Analysis in 1995-1997. He was also a research collaborator of SMA (Singapore MIT Alliance) research team in 1998-2001. Dr. Radhakrishnan is currently the Vice-President of IEEE Electron Devices Society. He was an Elected Member of the Board of Governors of IEEE Electron Devices Society (2011-2016), He is an IEEE EDS Distinguished Lecturer from 1997 onwards and serves as the Editor of IEEE Journal of Electron Devices (IEEE JEDS). He was Editor-in-Chief of IEEE EDS Newsletter (2013-17), Guest Editor to IEEE TDMR and the Editor of Journal of Semiconductor Technology and Science (JSTS) from 2002-2005. As a researcher, academician and technical consultant he works with various MNCs in Asia, Europe and USA. He continues to do extensive training on device analysis & reliability and ESD to various Industries, Universities and Research Centers. Dr. Radhakrishnan has given plenary and keynote talks at numerous major international conferences around the globe, and has given more than 100 Distinguished Lectures. He is a Fellow of IETE, Life Senior Member of IEEE, Member of EDFAS and ESDA. 

Address:Founder Director , NanoRel LLP -Technical Consultants , Singapore





Agenda

08:45 AM - Refreshments and Networking

 

09:45 AM - 10:30 AM: Interface Physics, Reliability and Analysis Challenges in Si Nanodevices by Dr. MK Radhakrishnan, EDS VP, CR,NANOREL, Singapore

You do not have to be an IEEE Member to attend. Refreshmen is free for all attendess. Please invite your friends and colleagues to take advantages of this Invited series of Distinguished Lectures. You need to register.



Co-sponsor by MTT/AP & ED/CAS Chapters