Heterogeneous Integration for High-Performance Computing and Data Centers
The High Performance Computing and Data Center chapter of the Heterogeneous Integration Roadmap presents the clear need for heterogeneous system integration that realizes systems-in-a-package (SiPs) that target the HPC and data center markets. The potential solutions and short-term, medium-term and longer-term challenges that are encountered in realizing these SiPs are addressed. Although, as in the past, the processor-memory performance gap remains a key driver for the overall system architecture, new factors that drive the need for heterogeneous integration in the HPC and data center markets have been emerging. These factors include technology limitations, new and emerging applications, and scaling needs for surmounting power dissipation, power delivery and package IO constraints.
Date and Time
Location
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Registration
- Date: 18 Jun 2020
- Time: 08:00 AM to 09:00 AM
- All times are (GMT-08:00) US/Pacific
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- Santa Clara, California
- United States
- Starts 23 May 2020 11:03 PM
- Ends 18 June 2020 08:57 AM
- All times are (GMT-08:00) US/Pacific
- No Admission Charge
Speakers
Dale of IBM Systems and a member of the IBM Academy of Technology
Biography:
Dale Becker received the B-EE degree from the University of Minnesota, MS-EE from Syracuse University and the PhD from the University of Illinois at Urbana Champaign. He is a Chief Engineer of Electronic Packaging Integration in IBM Systems and a member of the IBM Academy of Technology. His responsibility is the electrical system architecture of IBM Systems including the design of high-speed channels to enable the computer system performance and the power distribution networks for reliable operation of the integrated circuits that make up the processor subsystem. Dr. Becker has chaired the IEEE EPEPS Conference in 2010, 2014, and 2016 and has co-chaired the 2014 IEEE EMCS embedded conference on SIPI TPC as well as 2017 EMCS Global University Chair. He has been a distinguished lecturer in the EMC Society. He has patents on electrical design of computer systems and has presented papers in refereed journals and international conferences covering many aspects of electrical computer system design including power distribution analysis and design and modeling of signal and power distribution networks. He is an IEEE Fellow, an iNEMI Technical Committee member, and co-chairs the HI Roadmap Working Group on High-Performance Computing and Data Centers.
Kanad of State University of New York, Binghamton
Biography:
Kanad Ghose received the PhD degree from Iowa State University. He is currently a Distinguished Professor with the Computer Science Department, State University of New York, Binghamton, where he served as the Department Chair from 1998 to 2016. His research work has been funded by the NSF, DARPA, AFOSR as well as the industry (Intel, IBM, Lockheed-Martin, BAE Systems, SRC, NBMC, etc.). His current research interests include power-aware microarchitecture and systems ranging from ultra low-power sensors to high-performance processors and data centers. He has authored technical papers extensively in these areas. He holds 25 awarded patents, including four licensed patents. Kanad is a Fellow of the National Academy of Inventors and a member of the IEEE and ACM. He serves as the Site Director for the Center for Energy-Smart Electronics Systems, a Phase II NSF Industry-University Cooperative Research Center at Binghamton, the founding site, with three other university sites. He is co-chair of the HI Roadmap’s Working Group on HPC and Data Centers.