Nanoelectronics to Nanotechnology: Challenges and Directions

#(AI) #dynamical #modeling #and #simulation
Share

IEEE ED-S DL Talk 


The next generation of nanoelectronics device scaling for sub-14 nm CMOS technology (More Moore) has introduced bulk/SOI FinFETs and requires that the EOT scaling of gate dielectric beyond 0.7 nm. FinFET Reliability issues like Self-Heating has been a challenge that needs to be resolved. Additionally, current trends in Internet of Things (IoT) require the convergence of Nanoelectronics, Nanotechnology, Communication Technology and Information Technology. Integrated sensor systems monitoring environment, health care, water quality, vehicle traffic, smart cities are becoming the norm. Despite extended range of applications, low power requirement is the key to these nanosystems. Incorporation of
different nanodevices into these nanosystems with functionalities that do not necessarily scale according to "Moore&#39's Law,” but provide additional value in different ways (more than Moore), is necessary. Furthermore, nanoelectronic devices with extremely low power consumption allows a set of next generation devices for artificial intelligence hardware and neuromorphic applications. It is, therefore, important to get exposed to the current trends in circuit design architectures, device structures and fabrication, device and circuit relationship and design, reliability of new devices and processes. In this talk, some of the recent developments and trends in device design and fabrication of next generation electronics devices and IoT devices will be outlined. 



  Date and Time

  Location

  Hosts

  Registration



  • Date: 27 May 2020
  • Time: 09:30 PM UTC to 11:00 PM UTC
  • Add_To_Calendar_icon Add Event to Calendar
  • Virtual Online Zoom Meeting
  • Location:Please register at IEEE vTools
  • Global Webinar, New Jersey
  • United States

  • Contact Event Host
  • Dr. Ajay K. Poddar, Eamil: akpoddar@ieee.org

    Prof. Edip Niver, Email: edip.niver@njit.edu

    Prof. Durgamadhav Mishra, Email: dmisra@njit.edu

    Dr. Anisha M. Apte, Email:anisha_apte@ieee.org

     

  • Co-sponsored by IEEE North Jersey MTT/AP & ED/CAS Chapter
  • Starts 10 May 2020 02:00 PM UTC
  • Ends 27 May 2020 05:00 PM UTC
  • No Admission Charge


  Speakers

Prof. Durga Misra of Helen and John C. Hartmann Department of Electrical and Computer Engineering, NJIT, Newark, New Jersey, USA

Topic:

Nanoelectronics to Nanotechnology: Challenges and Directions

The next generation of nanoelectronics device scaling for sub-14 nm CMOS technology (More Moore) has introduced bulk/SOI FinFETs and requires that the EOT scaling of gate dielectric beyond 0.7 nm. FinFET Reliability issues like Self-Heating has been a challenge that needs to be resolved. Additionally, current trends in Internet of Things (IoT) require the convergence of Nanoelectronics, Nanotechnology, Communication Technology and Information Technology. Integrated sensor systems monitoring environment, health care, water quality, vehicle traffic, smart cities are becoming the norm. Despite extended range of applications, low power requirement is the key to these nanosystems. Incorporation of
different nanodevices into these nanosystems with functionalities that do not necessarily scale according to "Moore&#39's Law,” but provide additional value in different ways (more than Moore), is necessary. Furthermore, nanoelectronic devices with extremely low power consumption allows a set of next generation devices for artificial intelligence hardware and neuromorphic applications. It is, therefore, important to get exposed to the current trends in circuit design architectures, device structures and fabrication, device and circuit relationship and design, reliability of new devices and processes. In this talk, some of the recent developments and trends in device design and fabrication of next generation electronics devices and IoT devices will be outlined. 

Biography:

Prof. Durga Misra is a Professor in the Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, USA. His current research interests are in the areas of nanoelectronic/optoelectronic devices and circuits, especially in the area of nanometer CMOS gate stacks and device reliability. He is Fellow of IEEE. He is a Distinguished Lecturer of IEEE Electron Devices Society (EDS) and serving in the IEEE EDS Board of Governors. He is ,also, a Fellow of the Electrochemical Society (ECS). He received the Thomas Collinan Award from the Dielectric Science & Technology Division of ECS. He is also the winner of the Electronic and Photonic Division Award from ECS. He edited and co-edited more than 45 books and conference proceedings in his field of research. He has published more than 200 technical articles in peer reviewed Journals and in International Conference proceedings including 95 Invited Talks. He has graduated 19 PhD students and 40 MS students. He received the M.S. and Ph.D. degrees in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 1985 and 1988, respectively.

Email:

Address:Helen and John C. Hartmann Department of Electrical and Computer Engineering, New Jersey Institute of Technology (NJIT), Newark, New Jersey, United States





Agenda

  • Date: 27 May 2020
  • Time: 05:30 PM to 06:30 PM Eastern Time (US and Canada)
  • Join Zoom Meeting
    https://us02web.zoom.us/j/86048150132

    Meeting ID: 860 4815 0132
    Password: 746035
  • Join by Phone
    +13126266799 USA
    +16465588656, USA
     

 



Co-sponsored by IEEE North Jersey MTT/AP & ED/CAS Joint Chapter