Lecture on "Behavior Modelling Style of Verilog HDL"

#Verilog #HDL #VLSI #CASS #VNRVJIET #Behavioural #Modeling #Synthesis #Simulation
Share

On 19th June, 2020 Mr. K Naresh  gave a lecture on the topic “Behavior Modelling Style of Verilog HDL”.

Mr. K. Naresh started the lecture by explaining the basics, types and preferences of Verilog.

The speaker explained about the similarities between C and verilog HDL.

The session proceeded from explaining the differences between continuous assignment and procedural assignment.

He then showed us the types, their syntaxes and examples of procedural blocks followed by continuing to expand on the topic of procedural assignments. And gave a detailed explanation on blocking and non blocking assignments.

Mr. Naresh then spoke about advantages and disadvantages race condition.

The speaker also gave the details on level sensitive timing control and functions vs tasks and concluded the session by explaining the concept of regular delay control.


  Date and Time

  Location

  Hosts

  Registration


  • Date: 19 Jun 2020
  • Time: 11:00 AM to 01:00 PM
  • All times are (GMT+05:30) Asia/Calcutta
  • Add_To_Calendar_icon Add Event to Calendar
  • Hyderabad, Andhra Pradesh
  • India
  • Contact Event Host

  Speakers

Mr K Naresh Mr K Naresh of VNR Vignana Jyothi Institute of Engineering and Technology

Topic:

Behavior Modelling Style of Verilog HDL

Biography:

Assistant Professor, Department of ECE

Teaching Interests: Switching Theory and Logic Design, Linear and Digital IC, VLSI Design, Digital design Through Verilog, Low Power VLSI design, Electronic Measurements and Instrumentation, CPLD & FPGA Architectures & Applications

Email:




Agenda

This lecture aimed at explaining about  behavioral modeling. The basic idea is describe how a circuit should behave. For many reasons, behavioral modeling is considered highest abstraction level as compared to data-flow or structural models. The VHDL synthesizer tool decides the actual circuit implementation.


About 40 people attended this webinar and it helped the participants understand the significance of Verilog.The session was interactive and the speaker was enthusiastic  and encouraged the students to ask and clarify their doubts.