Lecture on "Structural Modelling Style of Verilog HDL"

#Structural #Modelling #Verilog #HDL #VLSI #Lecture #CASS #VNRVJIET
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On 22nd   June, 2020 Mr. CH Ganesh gave a lecture on the topic “Structural Modelling Style of Verilog HDL”

The speaker started the session by giving a brief explanation about the design of simple electronic circuit.

Then he proceeded by showing us the design of VLSI circuit.

It was explained that the design of VLSI circuit starts from getting a specification to simplifying that specification and instead of passing to manual design it goes to CAD (Computer aided design) and from there it goes to simulation followed by synthesis. From there it is passed to gate level net list and layout.

Futher it was taught that programming will have certain styles like behavioral, data flow and structural.

The speaker continued the session that specifications can be simplified using either truth table or Boolean equation or in terms of logic diagram.

The speaker showed the process of creating full adder design using the AND gate with the help of tool


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  • Date: 22 Jun 2020
  • Time: 11:00 AM to 01:00 PM
  • All times are (GMT+05:30) Asia/Calcutta
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  • Hyderabad, Andhra Pradesh
  • India
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  Speakers

Mr Ch Ganesh of VNR Vignana Jyothi Institute of Engineering and Technology

Biography:

Assistant Professor, Dept. of ECE




Agenda

The goal of the lecture was to familiarize the participants with the basics of verilog HDL and thus explaining us about the full adder design using logic gates. The structural modelling style is the lowest level of abstraction obtained using logic gates. Similar to schematic or circuit diagrams of the digital circuit, Verilog uses primitive gates to compile and synthesize the program. Of course, this abstraction can't be understood by humans.


About 43 people attended this session. It helped the participants to understand the depth of concepts of verilog HDL. This was a very interactive session and doubts were highly encouraged.


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