Sorin Cotofana of TU Delft

In this presentation we argue and provide Non-Equilibrium Green's Function Landauer formalism-based simulation evidence that in spite of Graphene's bandgap absence, Graphene Nanoribbons (GNRs) can provide support for energy effective computing.  We start by demonstrating that: (i) band gap can be opened by means of GNR topology and (ii) GNR's conductance can be mold according to some desired functionality, i.e., 2- and 3-input AND, NAND, OR, NOR, XOR, and XNOR, via shape and electrostatic interaction. Afterwards, we introduce a generic GNR based Boolean gate structure composed of a pull-up GNR performing the gate Boolean function and a pull-down GNR performing the gate inverted Boolean function, and, by properly adjusting GNRs' dimensions and topology, we design and evaluate by means of SPICE simulations inverter, buffer, and 2-input GNR based AND, NAND, and XOR gates. When compared with state-of-the-art graphene FET and CMOS based counterparts the GNR-based gates outperform its challengers, e.g., up to 6x smaller propagation delay, 2 orders of magnitude smaller power consumption, while requiring 1 to 2 orders of magnitude smaller active area footprint than 7nm CMOS equivalents. Finally, to get better inside in the practical implications of the proposed approach, we present Full Adder (FA) and SRAM cell GNR designs, as they are currently fundamental components for the construction of any computation system. For an effective FA implementation, we introduce a 3-input MAJORITY gate, which apart of being able to directly compute FA's carry-out is an essential element in the implementation of Error Correcting Codes codecs, that outperforms a 7nm CMOS equivalent Carry-Out calculation circuit by 2 and 3 orders of magnitude in terms of delay and power consumption, respectively, while requiring 2 orders of magnitude less area. The proposed FA exhibits 6x smaller delay, 3 orders of magnitude less power consumption, while requiring 2 orders of magnitude less area than a 7 nm FinFET CMOS counterpart. However, because of the effective carry-out circuitry, a GNR-based n-bit Ripple Carry Adder, whose performance is linear in the Carry-Out path delay, will be 108x faster than an equivalent CMOS implementation. The GNR-based SRAM cell provides a slightly better resilience to DC-noise characteristics, while performance-wise has a 3x smaller delay, consumes 2 orders of magnitude less power, and requires 1 order of magnitude less area than the CMOS equivalent. These results clearly indicate that the proposed GNR-based approach is opening a promising avenue towards future competitive carbon-based nanoelectronics.

Biography:

Sorin Cotofana (M'93-SM'00-F'17) received the MSc degree in Computer Science from the "Politechnica" University of Bucharest, Romania, and the PhD degree in Electrical Engineering from Delft University of Technology, The Netherlands. He is currently with the Electrical Engineering, Mathematics and Computer Science Faculty, Delft University of Technology, Delft, the Netherlands. His current research is focused on: (i) the design and implementation of dependable/reliable systems out of unpredictable/unreliable components; (ii) ageing assessment/prediction and lifetime reliability aware resource management; and (iii) unconventional computation paradigms and computation with emerging nano-devices. He (co-)authored more than 250 papers in peer-reviewed international journal and conferences, and received 12 international conferences best paper awards, e.g., 2012 IEEE Conference on Nanotechnology, 2012 ACM/IEEE International Symposium on Nanoscale Architectures, 2005 IEEE Conference on Nanotechnology, 2001 International Conference on Computer Design. He served as Associate editor for IEEE Transactions on CAS I (2009-2011), IEEE Transactions on Nanotechnology (2008-2014), member of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems Senior Editorial Board (2016-2017), Steering Committee member for IEEE Transactions on Multi-Scale Computing Systems (2014-2018), Chair of the Giga-Nano IEEE CASS Technical Committee (2013-2015), and IEEE Nano Council CASS representative (2013-2014) and has been actively involved as reviewer, Technical Program Committee (TPC) member, and TPC (track) and general (co)-chair, in the organization of numerous international conferences. He is currently Associate Editor in Chief and Senior Editor for IEEE Transactions on Nanotechnology and Associate Editor for IEEE Transactions on Computers. He is a Fellow IEEE member (Circuits and System Society (CASS) and Computer Society) and a HiPEAC member.

Address:Brazil

David Allstot of Oregon State University

Biography:

David J. Allstot holds a B.S., Engineering Science from University of Portland, Portland, OR, 1969, a M.S., Electrical and Computer Engineering from Oregon State University, Corvallis, OR, 1974 and a Ph.D., Electrical Engineering and Computer Science from University of California, Berkeley, CA, 1979. He has held several industrial and academic positions including the Boeing-Egtvedt Chair at the Univ. of Washington from 1999 to 2012 and Chair of EE from 2004 to 2007. In 2012 he was a Visiting Professor of EE at Stanford and from 2013 to 2016, he held a three-year appointment as the MacKay Professor in Residence in EECS at UC Berkeley. Since June 2017, he has been a Professor in EECS at Oregon State University. He has advised about 65 M.S. and 40 Ph.D. graduates, published more than 300 papers, and received awards for teaching and research including the 1980 IEEE W.R.G. Baker Award, 1995 and 2010 IEEE Circuits and Systems Society (CASS) Darlington Award, 1998 IEEE ISSCC Beatrice Winner Award, 2004 IEEE CASS Charles A. Desoer Technical Achievement Award, 2005 SRC Aristotle Award, 2008 Semiconductor Industries Association University Research Award, 2011 IEEE CASS Mac Van Valkenburg Award, and 2015 IEEE Trans. on Biomedical Circuits and Systems Best Paper Award. He has been active in service to the IEEE CASS and Solid-State Circuits Societies throughout his career.