Lecture on "Synthesizable Verilog HDL for FSM"
On 23rd June ,2020 Ms. K. Swetha Reddy gave a lecture on the topic “Synthesizable Verilog HDL for FSM”.
Ms. K. Swetha Reddy took a problem statement and she taught to develop it through Verilog HDL.
Ms. K. Swetha Reddy started by explaining about an FSM ,what it consists of and types ,the states .
The speaker then explained about mealy based FSM, Moore based FSM ,FSM design procedure .
The session proceeded from classification of state encoding of FSM to problem statements on different sequence detectors analysis of inputs and outputs with and without overlapping .
The speaker further discusses about applications like bus arbiter ,car speed controller rotary combination lock etc which can be implemented by FSM.
It further proceeds with Verilog coding guidelines and examples for reset conditions.
The speaker ends the session with coding guidelines.
Date and Time
Location
Hosts
Registration
- Date: 23 Jun 2020
- Time: 11:00 AM to 01:00 PM
- All times are (UTC+05:30) Chennai
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- Hyderabad, Andhra Pradesh
- India
Speakers
Ms K Swetha Reddy of VNR Vignana Jyothi Institute of Engineering and Technology
Biography:
Assistant Professor, Dept. of ECE
Agenda
This lecture aimed at explaining that we can quantify the capabilities of various FSM coding styles . The FSM coding style should be easily modifiable to change state encodings and FSM styles.it describes the circuit of a finite number of unique states, what it consists of and design procedure.
About 50 people attended this webinar and it helped the participants understand the significance of Verilog. The session was interactive and the speaker was enthusiastic and encouraged the students to ask and clarify their doubts and very keenly explained.
Media
| SS 1 | 49.49 KiB | |
| SS 2 | 37.23 KiB | |
| SS 3 | 51.97 KiB |