ERIC PERFECTO of IBM

Abstract:
Moore's Law has reached a limit due to scaling limitations, increased performance demands and defect reduction requirements for each subsequent node, resulting in higher development and wafer fab/equipment costs. New nodes are no longer cost effective. However, innovations in packaging are driving overall system performance through improvements in interconnection wiring ground rules and greater I/O connectivity between the chip and the package. Two main packaging technologies are emerging as winners in this new interconnection race: 2.5D and Fan-Out Wafer Level Packaging. This presentation will provide you with increased understanding of these technologies, utilizing the new Heterogeneous Integration Roadmap released on 2019 as the source.

Biography:

Eric Perfecto  has 38 years of experience working in microelectronics, first at IBM working in the development of multi-level Cu-polyimide advanced packages for high-end systems, followed by the development of the UBM and Pb-free solder processes and yields for flip chip in 2D and 3D packages. As part of the IBM Microelectronics Division divestiture, Eric moved to GLOBALFOUNDRIES where he established a Si Photonics packaging assembly line. He returned to IBM  Research at Albany working on heterogeneous integration packaging.   Eric holds an M.S. in Chemical Engineering from the University of Illinois and M.S. in Operations Research from Union College.  An author of 79 technical papers and four book chapters, he served as the 57th ECTC General Chair. He is an IEEE Fellow, an elected BoG member of the IEEE Electronics Packaging Society (EPS) and an EPS Distinguished Lecturer.