Timing Closure at Advanced Nodes
This talk describes some of the challenges in timing closure at advanced nodes. The first half of the presentation gives an overview of static timing analysis (STA), what are corners, what are parasitics, and what kind of checks are checked in STA. The presentation also provides a brief explanation of how interconnect delay is computed, and what are late and early paths.
The second half of the talk focuses on some of the issues pertaining to advanced nodes, namely variation, inversion and run time complexity. Variation can be local and global. Inversion can cause non-intuitive corners to have worse times. And run time complexity is getting everyone worried about the cost of doing STA.
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- 141 Warren St
- Newark, New Jersey
- United States 07102
- Building: ECEC
- Room Number: 202
- Click here for Map
- Contact Event Host
- You can contact Ajay Poddar at 201-560-3806 or Edip Niver at 973-596-3542
- Co-sponsored by ED/CAS & MTT/AP-S
- Starts 13 February 2014 01:15 AM UTC
- Ends 05 March 2014 08:00 PM UTC
- No Admission Charge
Speakers
Jayaram Bhasker of eSilicon Corporation
Timing Closure at Advanced Nodes
This talk describes some of the challenges in timing closure at advanced nodes. The first half of the presentation gives an overview of static timing analysis (STA), what are corners, what are parasitics, and what kind of checks are checked in STA. The presentation also provides a brief explanation of how interconnect delay is computed, and what are late and early paths. The second half of the talk focuses on some of the issues pertaining to advanced nodes, namely variation, inversion and run time complexity. Variation can be local and global. Inversion can cause non-intuitive corners to have worse times. And run time complexity is getting everyone worried about the cost of doing STA.
Biography:
Dr. Bhasker is a distinguished author and expert in the area of hardware description languages and RTL synthesis. He has published a number of papers in journals and conferences, and has authored numerous books on VHDL, Verilog, SystemVerilog, SystemC and more recently on static timing analysis. Bhasker has served on several conference committees including the Design Automation Conference, Design & Verification Conference (DVCon) and VHDL International Users Forum (VIUF). He has been the chair of two working groups: the IEEE 1076.6 VHDL Synthesis Working Group and the IEEE 1364.1 Verilog Synthesis Working Group and a major contributor to the IEEE Std 1076.3 NUMERIC packages.
Bhasker is currently an Architect at eSilicon Corporation in Allentown, PA, where he guides physical design methodology for all chips that tapeout at eSilicon. He has also been a Senior Architect at Cadence Design Systems, and a Distinguished Member of the Technical Staff at Bell Laboratories. He is the recipient of the Honeywell Excel Pioneer Award (1987) and the IEEE Computer Society Outstanding Contribution Award (2005). Bhasker holds a Ph.D. degree in Computer Science from the University of Minnesota and an M.Tech and B.Tech. from Indian Institute of Technology, New Delhi.
Email:
Address:1605 N. Cedar Crest Blvd, Suite 615, , Allentown, Pennsylvania, United States, 18103
Jayaram Bhasker of eSilicon Corporation
Timing Closure at Advanced Nodes
Biography:
Email:
Address:Allentown, Pennsylvania, United States
Jayaram Bhasker of eSilicon Corporation
Timing Closure at Advanced Nodes
Biography:
Email:
Address:Allentown, Pennsylvania, United States
Jayaram Bhasker of eSilicon Corporation
Timing Closure at Advanced Nodes
Biography:
Email:
Address:Allentown, Pennsylvania, United States
Agenda
5-6pm Seminar
Room ECEC 202, NJIT Campus
You don't have to be an IEEE member to attend.