Power Integrity: Ensuring Robust End-to-End Power Delivery-

#power #delivery #solution #for #high-performance #microprocessors #(xPUs #FPGA #ASIC #etc.)

A robust power delivery solution for high-performance microprocessors (xPUs, FPGA, ASIC etc.) requires voltage at the active junction to be within the specified range to ensure timing closure, and also requires the VR and PDN to support ever increasingly complex power management features. The source of power comes from conversion circuitry which usually transforms higher voltage to a much more granularly regulated form lower than 1V DC in most cases, and then is distributed through board, package and on-die network and decoupling all the way to the active circuits. In the past, power designers and signal/power integrity engineers have worked together to address the conversion and distribution challenges in frequencies ranging from KHz to GHz, but the methodologies used by the two groups are decoupled. In today’s high-performance computing processors, many of which are used in machine learning, artificial intelligence and cloud applications, we have seen transformations of computing architecture that result in changes in power demand signatures, and thus call for new ways of power delivery solution. To address these new challenges, a holistic approach that combines power conversion together with power integrity design becomes a must. In this presentation, we will explore the risks and opportunities in this area and share our considerations in practical designs.