Algorithm-model-hardware codesign for accelerating deep neural network inference and training

#Algorithm #neural #networks #DNN #interference

Presenter: Professor Mieszko Lis (University of British Columbia)

Accelerating DNN inference in hardware has been extensively explored in the recent years, and many accelerator architectures have been proposed. How much performance and efficiency is still left for future researchers?

In this talk, Professor Mieszko will argue that extracting significantly more performance requires us to design multiple system components — algorithms, models, and hardware — to work together. Architects need to understand not just the computations that DNN inference and training perform, but also how models are designed and how optimization algorithms train those models.

He will discuss examples of this approach: an efficient sparse-from-scratch training algorithm, and a technique that modifies existing CNNs by fusing adjacent convolutional layers. Both of these achieve 4–6× speedups at iso-accuracy, but neither would be possible without co-designing the algorithm, the model, and the hardware accelerator.