Algorithm-model-hardware codesign for accelerating deep neural network inference and training

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Presenter: Professor Mieszko Lis (University of British Columbia)

Accelerating DNN inference in hardware has been extensively explored in the recent years, and many accelerator architectures have been proposed. How much performance and efficiency is still left for future researchers?

In this talk, Professor Mieszko will argue that extracting significantly more performance requires us to design multiple system components — algorithms, models, and hardware — to work together. Architects need to understand not just the computations that DNN inference and training perform, but also how models are designed and how optimization algorithms train those models.

He will discuss examples of this approach: an efficient sparse-from-scratch training algorithm, and a technique that modifies existing CNNs by fusing adjacent convolutional layers. Both of these achieve 4–6× speedups at iso-accuracy, but neither would be possible without co-designing the algorithm, the model, and the hardware accelerator.

Registration is required for access to the Zoom meeting link. This way we can ensure quality discussions of participants from industry and education.



  Date and Time

  Location

  Hosts

  Registration



  • Date: 27 Apr 2021
  • Time: 01:00 PM to 03:00 PM
  • All times are Canada/Pacific
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Zoom Meeting

  • Starts 26 April 2021 12:00 PM
  • Ends 27 April 2021 01:00 PM
  • All times are Canada/Pacific
  • No Admission Charge


  Speakers

Speaker 1

Topic:

Mieszko Lis

Professor Mieszko Lis has served on the ECE faculty at UBC since 2014. He has broad interests in computer architecture and systems, including accelerators for machine learning, computation, and graphics, memory systems, coherence and consistency formalisms, hardware design methodologies, programming languages, and applications of computing to scientific fields like biochemistry and immunology. Before joining academia, he co-founded two startups, Sandburst Corp and Bluespec Inc, where he co-designed the high-level HDL Bluespec.