One Week SDP On VLSI DESIGN FLOW Using Cadence Software with Hands-On Experience

#Workshops

The aim of this workshop is to provide hands-on experience on the state-of-the-art Cadence EDA tools for VLSI Design. The participants will have exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and Extraction. The workshop includes practice sessions on the Cadence design and simulation tools (Encounter, RTL Compiler, Virtuoso, Spectre, Assura, and Incisive).

Workshop Topics
 Introduction to Cadence and its various tools.
 Basics of Analog design using Cadence Virtuoso.
 Introduction to Physical Verification, DRC/LVS by Assura.
 Extraction of RC Components and Generation of GDSII file.
 Implementation of NC Launch and RTL Compiler for Digital Circuit using Verilog.
 Synthesis and Physical Design by Encounter i.e., Digital implementation

• Start time: 22 Mar 2021 03:30 AM UTC
• End time: 27 Mar 2021 10:30 AM UTC
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• Geethanjali College of Engineering and Technology
• Cheeryal Village and Keesara Mandal
• Hyderabad, Andhra Pradesh
• India

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• Starts 18 March 2021 03:30 AM UTC
• Ends 20 March 2021 06:30 PM UTC
• No Admission Charge

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VLSI design, the methodology makes extensive use of CAD techniques, including multilevel simulation for all tasks associated with design simulation and layout. The methodology is intended to totally verify the system during the design phase, prior to the release of VLSI components for fabrication. Today many companies like Texas Instruments, Infineon, Alliance Semiconductors, Cadence, Synopsys, Celox Networks, Cisco, Micron Tech, National Semiconductors, ST Microelectronics, Qualcomm, Lucent, Mentor Graphics, Analog Devices, Intel, Philips, Motorola, and many other firms have been established and are dedicated to the various fields in "VLSI" like Programmable Logic Devices, Hardware Descriptive Languages, Design tools, Embedded Systems, etc