IEEE EDS Distinguished Lecture by Prof. Marcelo Antonio Pavanell on "Compact Continuous Model of Drain Current and Transcapacintaces of Junctionless Nanowire Transistors""
IEEE EDS Distinguished Lecture by Prof. Marcelo Antonio Pavanell on "Compact Continuous Model of Drain Current and Transcapacintaces of Junctionless Nanowire Transistors""
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- Date: 27 May 2021
- Time: 06:00 PM to 07:30 PM
- All times are (GMT+05:30) Asia/Calcutta
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- IIT Kanpur
- Kanpur, Uttar Pradesh
- India 208016
Speakers
Marcelo Antonio Pavanello of Centro Universitário da FEI
Compact Continuous Model of Drain Current and Transcapacintaces of Junctionless Nanowire Transistors
In this talk, the compact continuous analytical models developed for drain current and transcapacitances of Junctionless Nanowire Transistors (JNTs) will be presented. The models will be compared with TCAD numerical simulations and experimental data, showing good agreement in all regimes of operation. The necessary adaptions on the drain current model for the description of JNT characteristics at high temperatures will also be presented and validated.
Biography:
Marcelo Antonio Pavanello (S´99-M´02-SM´05) received the Electrical Engineering degree from FEI University in 1993, receiving the award “Instituto de Engenharia” given for the best student among all the modalities of engineering programs offered at FEI. He received the M. Sc. and Ph. D. degrees in 1996 and 2000, respectively, in Electrical Engineering (Microelectronics) from University of São Paulo, Brazil. From August to December 1998 he was with Laboratoire de Microélectronique from Université Catholique de Louvain (UCL), Belgium, working in the fabrication and electrical characterization of novel channel-engineered Silicon-On-Insulator (SOI) transistors. From 2000 to 2002 he was with the Center of Semiconductor Components and Nanotechnologies, State University of Campinas, Brazil, where he worked as a post-doctoral researcher in the development of a CMOS n-well process. Since 2003 he joined FEI University, where he is now Full Professor at Electrical Engineering Department. In 2008 he has been with UCL as a visiting professor. Between 2010 and 2020 he also served as Vice-Rector for Teaching and Research at FEI.
Dr. Pavanello is Senior Member of the IEEE and Brazilian Microelectronics Society. He is also Researcher Associated to the National Council for Scientific Development (CNPq), Brazil. Since 2007 he serves as IEEE Electron Devices Society (EDS) Distinguished Lecturer and has been nominated to the Compact Modeling Technical Committee (CMTC) of EDS in 2018. In 2019 he has been assigned as Editor for Process and Device Modeling of IEEE Transactions on Electron Devices journal.
He is author or co-author of more than 400 technical papers in peer-reviewed journals and conferences, and author/editor of 6 books. Dr. Pavanello coordinates several research projects fomented by Brazilian agencies like FAPESP, CNPq and Capes. He also supervised several PhD dissertations, MSc thesis and undergraduate projects in Electrical Engineering.
His current interests are the compact modeling, fabrication, electrical characterization and simulation of SOI CMOS transistors with multiple gate configurations and silicon nanowires; the wide temperature range of operation of semiconductor devices; the digital and analog operation of novel channel-engineered SOI devices and circuits.
Email:
Address:Department of Electrical Engineering, Centro Universitário da FEI, Sao Paulo, Sao Paulo, Brazil