Number of Oscillation Cycles (NOC): A New Paradigm for VCO-based Comparison for ADC

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Distinguished lecture on

Number of Oscillation Cycles (NOC): A New Paradigm for VCO-based Comparison

By Prof. Qiang Li, UESTC, Chengdu, China

Abstract:

SAR ADCs are coming of age due to the mostly digital implementations where the benefit of advanced CMOS tech- nologies can be generally brought into ADC designs. Time-domain signaling is also promising since the speed and time resolution are both scaling favorable. Therefore, the SAR ADCs with time-based comparator have attracted significant interest in recent years. Nevertheless, comparing with oversampled converters where the unique property of VCO, the first-order noise shaping, has been used to enhance the system, Nyquist converters uses only the bit decision of time-base comparison. This talk introduces the concept of oscillation-cycle information in VCO-based comparators. With rigorous analysis, the number of oscillation cycles (NOC) can be generally exploited as a parallel coarse quantization with a large signal, and/or as a quantitative indication of metastability with a small signal. Moreover, the NOC is inherent and of little cost in hardware, power and area. The demonstrated VCO ADCs exhibit significantly enhanced linearity and robustness, comparing with their voltage-domain counterparts. This talk discusses also a closed-form metastability analysis of VCO-based comparator, introducing the metastability depth as a quantitative measure of metastability.


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  • IIT Delhi
  • Delhi, Delhi
  • India
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  • IEEE SSCS DELHI Chapter Chair : Rakesh Malik, Vervesemi Microelectronics Pvt.Ltd, INDIA

    Vice Chair: Dr. Shouri Chatterjee, IIT Delhi

    Secretary : Dr. Ankesh Jain, IIT Delhi

  • Co-sponsored by IIT delhi
  • Starts 11 March 2021 07:10 AM UTC
  • Ends 28 March 2021 12:30 PM UTC
  • No Admission Charge

  Speakers

Dr. Qiang Li

Topic:

Number of Oscillation Cycles (NOC): A New Paradigm for VCO-based Comparison

Abstract:

SAR ADCs are coming of age due to the mostly digital implementations where the benefit of advanced CMOS tech- nologies can be generally brought into ADC designs. Time-domain signaling is also promising since the speed and time resolution are both scaling favorable. Therefore, the SAR ADCs with time-based comparator have attracted significant interest in recent years. Nevertheless, comparing with oversampled converters where the unique property of VCO, the first-order noise shaping, has been used to enhance the system, Nyquist converters uses only the bit decision of time-base comparison. This talk introduces the concept of oscillation-cycle information in VCO-based comparators. With rigorous analysis, the number of oscillation cycles (NOC) can be generally exploited as a parallel coarse quantization with a large signal, and/or as a quantitative indication of metastability with a small signal. Moreover, the NOC is inherent and of little cost in hardware, power and area. The demonstrated VCO ADCs exhibit significantly enhanced linearity and robustness, comparing with their voltage-domain counterparts. This talk discusses also a closed-form metastability analysis of VCO-based comparator, introducing the metastability depth as a quantitative measure of metastability.

Biography:

Dr. Qiang Li is a professor at the Institute of Integrated Circuits and Systems (IICS), University of Electronic Science and Technology of China (UESTC), Chengdu, China. He received the B.Eng. degree in Electrical Engineering from Huazhong University of Science and Technology (HUST), Wuhan, China, in 2001, and the Ph.D. degree from Nanyang Technological University (NTU), Singapore, in 2007.

He has been working on analog/RF and mixed-signal circuits in both academia and industry. In 2001-2002, he was an RTP analog design engineer at the Centre for Wireless Communications (now I2R, A-STAR), Singapore. In 2006- 2008, he was a senior engineer and project leader at the Institute of Micro- electronics, A-STAR, Singapore. In 2008-2009, he was a Technical Consultant at the OKI Techno Centre (Singapore) Pte. Ltd. In 2011-2014, he was an Associate Professor at the Aarhus University, Denmark. He was the Vice Dean of the School of Microelectronics and Solid-State Electronics, UESTC, during 2014-2018. He is the founding head of the Institute of Integrated Circuits and Systems of UESTC. His research interests include low-voltage and low-power analog/RF circuits, data converters, and mixed-mode circuits for biomedical and sensor interfaces.

Dr. Li was a recipient of the Young Changjiang Scholar award in 2015, UESTC Teaching Excellence award in 2011 and Service Excellence award in 2018. He serves on the Technical Program Committees of ESSCIRC and ASSCC, the Student Research Preview (SRP) committee of ISSCC, and was the TPC Chair of IEEE 2018 APCCAS. He was/is a Guest Editor of IEEE Transactions on Circuits and Systems I (TCAS-I) and an Associate Editor of IEEE Open Journal of Circuits and Systems. He is the founding chair of IEEE SSCS/CASS Chengdu Joint Chapter.




Agenda

Distinguished lecture on

Number of Oscillation Cycles (NOC): A New Paradigm for VCO-based Comparison