Prof. Jesús A. del Alamo of Massachusetts Institute of Technology, USA

Much has been written about “The End of Moore’s Law” for over a decade. The term evokes a picture of stalled computing performance. Reality is far from this doomsday scenario and the outlook of information processing technology appears brighter than ever. Certainly, as transistor footprint scaling is quickly approaching a regime in which “smaller is no longer better,” a radical redirection is mandatory. The new path is the third dimension, piling transistors on top of each other in a 3D construction. The promise goes beyond the integration of more transistors per unit area to keep the economic incentives behind Moore’s Law. The third dimension opens new possibilities to bring together logic and memory and break the “memory wall”, the current bottleneck for system performance. Intimate memory and logic integration will also enable artificial intelligence chips capable of efficiently processing very large data sets. This talk will outline opportunities and challenges for future IC technologies.

Biography:

Jesús A. del Alamo is the Donner Professor and Professor of Electrical Engineering at Massachusetts Institute of Technology. He obtained a Telecommunications Engineer degree from Polytechnic University of Madrid and MS and PhD degrees in Electrical Engineering from Stanford University. In 1985 he joined Nippon Telegraph and Telephone LSI Laboratories in Japan and since 1988 he has been with the Department of Electrical Engineering and Computer Science of Massachusetts Institute of Technology. From 2013 until 2019, he served as Director of the Microsystems Technology Laboratories at MIT. His current research interests are focused on nanoelectronics based on compound semiconductors and ultra-wide bandgap semiconductors and novel ionic devices for artificial intelligence accelerators.

Prof. del Alamo was an NSF Presidential Young Investigator. He is a member of the Royal Spanish Academy of Engineering and Fellow of the Institute of Electrical and Electronics Engineers, the American Physical Society and the Materials Research Society. He is the recipient of the Intel Outstanding Researcher Award in Emerging Research Devices, the Semiconductor Research Corporation Technical Excellence Award, the IEEE Electron Devices Society Education Award, the University Researcher Award by Semiconductor Industry Association and Semiconductor Research Corporation, the IPRM Award and the IEEE Cledo Brunetti Award. He currently serves as Editor-in-Chief of IEEE Electron Device Letters. He is the author of “Integrated Microelectronic Devices: Physics and Modeling” (Pearson 2017, 880 pages), a rigorous and up to date description of transistors and other contemporary microelectronic devices. 

Email:

Address:Massachusetts Institute of Technology, 77 Massachusetts Ave., Rm. 38-246 Cambridge, MA, Massachusetts, India, 02139