North Jersey Section and PES/IAS Life Grade Luncheon

#Silicon-Gate #Integrated #Circuit #industry
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Silicon-Gate

An informal presentation on the invention and development of the Silicon-Gate process and its paradigm shifting impact on the Integrated Circuit industry by Dr. Robert Kerwin.




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  • 16 Eagle Rock Avenue
  • East Hanover, New Jersey
  • United States 07936
  • Building: Hanover Manor
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  Speakers

Dr. Robert Kerwin

Topic:

Silicon-Gate

An informal presentation on the invention and development of the Silicon-Gate process and its paradigm shifting impact on the Integrated Circuit industry.

Biography: Robert Kerwin is currently an independent consultant in electronics technology, intellectual property management, and quality management practices. In April, 1994 he retired from AT&T as General Manager of the Intellectual Property Division. Prior to that he had been Manager, Corporate Quality at AT&T after twenty two years experience at AT&T Bell Laboratories.

At AT&T Bell Laboratories, Dr. Kerwin was a member of Technical Staff in the Electronic Component Processes Laboratory (1964-1971), supervised the Photolithography Development Group (1971-1974), supervised the Murray Hill Integrated Circuit Design Capability Line responsible for the development of CMOS processing technology (1974-1980), and headed the Component Quality and Reliability Department responsible for reliability assurance of all electronic components made by or purchased for AT&T (1980-1986).

Dr. Kerwin holds a B.S. degree in Chemistry from Boston College, an M.S degree in Chemistry from the Massachusetts Institute of Technology, and a Ph.D. degree in Chemistry from the University of Pittsburgh. Prior to joining AT&T Bell Laboratories, he was a Research Fellow in the Polymer Studies Group at the Mellon Institute.

He is a Bell Laboratories Fellow, a Fellow of the American Institute of Chemistry, a member of the Society of Sigma Xi, the American Association for the Advancement of Science, and the Institute Electrical and Electronic Engineers. In 1994 he received the Jack A Morton Award from the IEEE “For Outstanding Contributions in the Field of Solid State Devices”, and Inventor of the Year Award from the New Jersey Inventors Hall of Fame.
He holds fifteen patents on microelectronics materials and processes, including the fundamental silicon-gate process used in all semiconductor memory and microprocessor devices. He has published fifteen papers and five book chapters on microelectronics technology, quality management principles and intellectual property management.

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Address:New Jersey, United States





Agenda

Attendees must apply with form provided by coordinator Ken Oexle at k.oexle@ieee.org or 973-386-1156.