Angad B Sachid of Indian Institute of Technology Bambay

Until now, a lot of effort has been put to improve the intrinsic delay of the transistors. With scaling the channel resistance and the gate to channel capacitance are decreasing. However, the external resistances like the extension region resistance and contact resistance, and the external capacitances like outer fringe capacitance and gate-to-contact capacitance have become a larger fraction of the total resistance and capacitance of the device. The interconnect capacitance is also becoming a larger fraction of the total load capacitance of the circuit. In this regard, decreasing the external resistances and capacitances has become more important than improving the intrinsic delay of the device. At the current and future technology nodes, improving the intrinsic delay will have diminishing returns due to poor extrinsic delay. Variability is one of the important reasons for non-scaling of the supply voltage. Variation in the electrical parameters of the devices increases with scaling. Traditionally, Planar MOSFETs were optimized without any consideration given to the dependence of electrical parameters on the electrical width (WELEC) of the device. This assumption was true in planar devices isolated using shallow-trench isolation as all the dominant electrical parameters were functions of WELEC. On similar lines, most of the prior work in the area of scaling, parasitic resistance and capacitance reduction, and variability is concentrated on using Multi-Gate FETs as ‘replacement devices’ to Planar MOSFETs. By ‘replacement devices’, we mean that a device with width WELEC is replaced by another device with a width close to WELEC (width quantization may not allow an exact replacement). Hence, the same optimization strategies used in Planar MOSFETs were applied to optimize Multi-Gate FETs. As the devices are scaled, the certain parasitic capacitance components, like the corner capacitance in Planar MOSFETs, that were negligible in earlier technologies should now be considered while optimizing the devices. In addition to this, the resistance and capacitance of interconnects is increasing. The interconnect parasitics can no longer be neglected even in small circuits. In this part, Extremely-Thin SOI (ETSOI) MOSFET is used to illustrate the concepts pertaining to Planar MOSFETs. We present methods to co-optimize Multi-Gate FETs by considering various non-idealities present in the device, circuit and system-level environment that are realistic at sub-22 nm nodes to improve the overall performance. Hence, technology-circuit co-optimization strategies are presented to address device, circuit and system-level challenges at sub-22 nm nodes as increasing device parasitic resistance and capacitance, non-negligible interconnect capacitance, increasing power and power density, process variations in devices and interconnects, and non-scaling supply voltage. We will present the differences between the nature of parasitic resistance and capacitance components in planar and non-planar devices, and their impact on circuit performance. FinFETs are used to illustrate the concepts for non-planar Multi-Gate FETs. We look at the possible impact of using novel processes on the device and circuit performance, and scalability of planar and non-planar devices. We also optimize FinFETs on SOI and Bulk substrates to see if there are any major differences in applying the methodologies developed in this work with these two types of device implementations.

Biography: Angada B. Sachid received the B.Tech. degree in electronics and communication engineering from
the National Institute of Technology, Kurukshetra, India, in 2003. Since July 2005, he has been
working toward the Ph.D. degree (expected to graduate in July 2010) in the Department of Electrical
Engineering, Indian Institute of Technology Bombay, Mumbai, India. From 2003 to 2005, he was a Scientist
with the VLSI Division of Advanced Numerical Research and Analysis Group, DRDO, India, where he worked
on the design and implementation of telecommunication SOCs and low power system design.
In 2007, he was a Summer Intern with the Taiwan Semiconductor Manufacturing Company,
where he worked on NBTI reliability, gate leakage modeling and 45 nm GP node device optimization.
He has given invited talks at IBM T. J. Watson Research Center, Intel Circuit Research Labs,
Stanford University, University of California Berkeley etc. His research interests include
technology-circuit co-design using novel devices like ETSOI MOSFETs and Multi-Gate FETs,
variability-aware-device design, novel devices and circuits for ultra-low power sub-0.5-V operation,
static and dynamic RAMs, impact of scaling on different design styles, non-charge based devices,
secure communication circuits and systems, digital and analog circuits in weak inversion,
and error-resilient circuits. His work on technology-aware design for sub-45 nm nodes was
awarded the Best Paper Award at the Intel Asia Academic Forum in 2008.
He is currently one of the eight finalists for the TSMC Outstanding Research Award 2010
and is nominated for the INAE Young Engineer Award 2010. He has served as the reviewer
for IEEE Transactions on Electron Devices, International VLSI Conference, VLSI Design
and Test Conference, and IETE journal for the last 3 years.

Address:EE Dept., IIT Bombay, Mumbai, Maharashtra, India

Angad B Sachid of Indian Institute of Technology Bambay

Biography:

Address:Mumbai, Maharashtra, India