UPDATED DATE: Asynchronous SAR ADC: Past, Present and Beyond
IEEE Solid-State Circuits Society Distinguished lecture by Dr. Mike Shuo-Wei Chen.
Date and Time
- Date: 30 Nov 2021
- Time: 10:00 AM to 11:30 AM
- All times are US/Mountain
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Meeting ID: 960 6662 1739
- Calgary, Alberta
- Canada T2N1N4
- Starts 31 October 2021 05:41 PM
- Ends 30 November 2021 10:00 AM
- All times are US/Mountain
- No Admission Charge
Shuo Wei (Mike) Chen of University of Southern California (USC)
Asynchronous SAR ADC: Past, Present and Beyond
The demand of low-power and high-speed ADC has been escalating in the past decade due to emerging low-power applications with wide bandwidth requirement, including both wireless and wireline systems. Historically, the ADC in this targeted specification regime has been dominated by Flash topology, where all the level comparisons are accomplished in parallel. However, the associated complexity prevents it from a true low-power solution. More than a decade ago, the asynchronous successive approximation (SAR) architecture was proposed to minimize the overall converter complexity while improving the speed of the SAR search algorithm. The first proof-of-concept silicon prototype in 130nm CMOS achieved the order-of-magnitude improvement in power efficiency. Since then, this low power ADC architecture has been widely adopted for various power-constraint, high-speed (up to 10s’ GS/s), medium to high resolution applications. In this talk, we will review the evolution of this ADC architecture, including the recent trend and potential extensions based on asynchronous operation principles, leading to various hybrid ADC architectures.
Mike Shuo-Wei Chen is a professor in Electrical Engineering Department at University of Southern California (USC) and holds the Colleen and Roberto Padovani Early Career Chair position. He received the B.S. degree from National Taiwan University, Taipei, Taiwan, in 1998 and the M.S. and Ph.D. degrees from University of California, Berkeley, in 2002 and 2006, all in electrical engineering.
As a graduate student, he proposed and demonstrated the asynchronous SAR ADC architecture, which has been adopted in industry today for low-power high-speed analog-to-digital conversion products. After joining USC in 2011, he leads an analog mixed-signal circuit group, focusing on high-speed low-power data converters, frequency synthesizers, RF/mm-wave transceiver designs, analog circuit design automation, bio-inspired computing, non-uniformly sampled circuits and systems. From 2006 to 2010, he worked on mixed-signal and RF circuits for various wireless communication products at Atheros Communications (now Qualcomm).
Dr. Chen was the recipient of Qualcomm Faculty Award in 2019, NSF Faculty Early Career Development (CAREER) Award, DARPA Young Faculty Award (YFA) both in 2014, Analog Devices Outstanding Student Award for recognition in IC design in 2006 and UC Regents’ Fellowship at Berkeley in 2000. He also achieved an honorable mention in the Asian Paciﬁc Mathematics Olympiad, 1994. Dr. Chen has been serving as an associate editor of the IEEE Solid-State Circuits Letters (SSC-L), IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), as well as a TPC member in IEEE Solid-State Circuits Society conferences, notably the IEEE International Solid-State Circuits Conference (ISSCC), IEEE Symposium on VLSI Circuits (VLSIC), and IEEE Custom Integrated Circuits Conference (CICC).