Yiorgos Makris, IEEE Sr. Member, Professor, Department of Electrical and Computer Engineering, University of Texas at Dallas of University of Texas at Dallas

Abstract:

As the majority of design houses follow the globalized fabless semiconductor manufacturing business model to curtail cost, their products are exposed to a range of security and trustworthiness threats, such as Intellectual Property (IP) theft, unauthorized over-production and counterfeiting. Therefore, the ability to hide sensitive or proprietary portions of a design from a potentially untrusted foundry is becoming paramount for IP protection. Design obfuscation solutions, such as logic locking, which embed the secret IP within broader functionality through the use of a secret key, offer a certain level of protection against brute-force attacks, yet have been shown vulnerable to intelligent attacks, such as the clever use of a Boolean Satisfiability (SAT) solver. To prevent an untrusted fab from obtaining sensitive IP, an alternative approach could rely, instead, on completely redacting parts of the design from the fabricated silicon and reinstating them through post-manufacturing programming. While this idea is, in itself, rather straightforward, realizing it in a cost-effective manner is quite challenging. Indeed, using embedded Field Programmable Gate Arrays (eFPGAs) to implement the omitted portion of the function provides high security levels but results in significant area, power and performance overhead. Towards alleviating this overhead, we developed a Transistor-Level Programmable (TRAP) fabric and an extensive framework for designing and implementing cost-effective hybrid ASIC/Programmable Integrated Circuits (ICs), wherein sensitive IP can be protected through design redaction. In this presentation, we will discuss the design of the latest version of our TRAP fabric, the CAD tool-flow necessary for supporting such hybrid designs ASIC/Programmable ICs, and the protection that TRAP-based design redaction offers against both brute-force and intelligent attacks seeking to recover the redacted IP.

Biography:

Yiorgos Makris received the Diploma of Computer Engineering from the University of Patras, Greece, in 1995 and the M.S. and Ph.D. degrees in Computer Engineering from the University of California, San Diego, in 1998 and 2001, respectively. After spending a decade on the faculty of Yale University, he joined UT Dallas where he is now a Professor of Electrical and Computer Engineering, the Co-Founder and Site-PI of the NSF Industry University Cooperative Research Center on Hardware and Embedded System Security and Trust (NSF CHEST I/UCRC), as well as the Leader of the Safety, Security and Healthcare Thrust of the Texas Analog Center of Excellence (TxACE) and the Director of the Trusted and RELiable Architectures (TRELA) Research Laboratory. His research focuses on applications of machine learning and statistical analysis in the development of trusted and reliable integrated circuits and systems, with particular emphasis in the analog/RF domain. He serves as an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and has served as an Associate Editor for the IEEE Information Forensics and Security and the IEEE Design & Test of Computers Periodical, as a guest editor for the IEEE Transactions on Computers and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He also served as the 2016-2017 general chair and the 2013-2014 program chair of the IEEE VLSI Test Symposium. He is a recipient of the 2006 Sheffield Distinguished Teaching Award, Best Paper Awards from the 2013 IEEE/ACM Design Automation and Test in Europe (DATE'13) conference and the 2015 IEEE VLSI Test Symposium (VTS'15), as well as Best Hardware Demonstration Awards from the 2016 and the 2018 IEEE Hardware-Oriented Security and Trust Symposia (HOST'16 and HOST'18) and a recipient of the 2020 Faculty Research Award from the Erik Jonsson School of Engineering and Computer Science at UT Dallas.