Modular Implementation of the latest RFSoC chip from Xilinx
IEEE AP/MTT Mini Show
The paradigm shift from discrete components connected via parallel LVDS, or high-speed differential pairs on various mezzanine cards to an FPGA has shifted to a more integrated design. The latest generation of devices includes analog I/O and multi-core ARM processors with high-speed PHY protocol components hardened in the FPGA fabric. This design requires complex, multi-layer PCB modules with phase-coherent synchronization, multiple integrated power supplies, and advanced signal integrity techniques to provide full use of this SoC (System-on-Chip) technology. The presentation will illustrate key design criteria to properly implement system-on-chip technology for the latest COTS (Commercial-off-the-Shelf) modules. It will include a brief review of the previous FPGA technology, address the advantages of each system and conclude with the latest generation SoC design. The goal of the presentation is to help engineers navigate design constraints of highly integrated SoC's that need to be included in their systems.
Date and Time
Location
Hosts
Registration
-
Add Event to Calendar
- Hanover Manor
- 16 Eagle Rock Avenue
- East Hanover , New Jersey
- United States 07936
- Contact Event Host
- Co-sponsored by IEEE North Jersey Section
- Starts 01 September 2021 02:00 PM UTC
- Ends 07 October 2021 01:00 PM UTC
- No Admission Charge
Speakers
Bob Muro of Pentek Systems
Modular Implementation of the latest RFSoC chip from Xilinx
The paradigm shift from discrete components connected via parallel LVDS, or high-speed differential pairs on various mezzanine cards to an FPGA has shifted to a more integrated design. The latest generation of devices includes analog I/O and multi-core ARM processors with high-speed PHY protocol components hardened in the FPGA fabric. This design requires complex, multi-layer PCB modules with phase-coherent synchronization, multiple integrated power supplies, and advanced signal integrity techniques to provide full use of this SoC (System-on-Chip) technology.
The presentation will illustrate key design criteria to properly implement system-on-chip technology for the latest COTS (Commercial-off-the-Shelf) modules. It will include a brief review of the previous FPGA technology, address the advantages of each system and conclude with the latest generation SoC design. The goal of the presentation is to help engineers navigate design constraints of highly integrated SoC's that need to be included in their systems.
Biography:
Bob Muro is an Embedded Systems AE with over 25yrs of experience in the Test & Measurement industry specializing in RF & uWave, communications, and digital & analog electronics.
Email:
Address:Pentek Systems, , United States
Agenda
For further information contact:
IEEE NORTH JERSEY SECTION CHAIR & MTT/AP CHAPTER CHAIR – AJAY KUMAR PODDAR (201-560-3806),akpoddar@ieee.org
CHAIR - GENERAL-EXHIBITION: KIRIT DIXIT (201-669-7599), kdixit@ieee.org
CHAIR – TECHNICAL PROGRAMS: GEORGE KANNELL(973-261-1421),george.kannell@gd-ms.com
THERE IS NO CHARGE TO ATTEND THE SYMPOSIUM OR SHOW.