Channel Code Design for Beyond 5G: Primitive Rateless Codes
Designing and optimizing short block length codes have been recently attracted for being implemented on memory or power-constrained devices, mainly in the context of the Internet of Things applications and services. The rate matching procedure is crucial to support various requirements and adapt to varying channel conditions. Existing rate compatible (RC) codes are mainly constructed using puncturing and extending, which are shown to be sub-optimal for short block lengths. Designing RC codes for short messages that support bit-level granularity of the codeword size and maintain a large minimum Hamming weight at various rates is still open. In this talk, I will introduce primitive rateless (PR) codes, which are mainly characterized by a primitive polynomial of degree k over GF(2). We will see that PR codes can be represented by using 1) linear-feedback shift-registers (LFSR) and 2) Boolean functions. We characterize PR codes' average Hamming weight distribution and develop a lower bound on the minimum Hamming weight, which is very close to the Gilbert-Varshamov bound. An interesting result is that for any k, there exists at least one PR code that can meet this bound. Simulation results show that the PR code with a properly chosen primitive polynomial can achieve a similar block error rate (BLER) performance as the eBCH code counterpart. This is because while PR codes might have a slightly lower minimum Hamming weight than the eBCH code, it has a lower number of low-weight codewords. PR codes can be designed for any message length and arbitrary rate and perform close to finite block length bounds. They are rate-compatible and have a very simple encoding structure, unlike most rate-compatible codes designed based on puncturing a low-rate mother code, with a sub-optimal performance at various rates.
Date and Time
Location
Hosts
Registration
- Date: 31 Mar 2022
- Time: 05:00 PM to 06:00 PM
- All times are (UTC+11:00) Canberra
-
Add Event to Calendar
- Melbourne, Victoria
- Australia 3000
- Starts 01 March 2022 01:35 PM
- Ends 31 March 2022 04:35 PM
- All times are (UTC+11:00) Canberra
- No Admission Charge
Speakers
Dr. Mahyar Shirvanimoghaddam
Channel Code Design for Beyond 5G: Primitive Rateless Codes
Biography:
Mahyar Shirvanimoghaddam is a Senior Lecturer at the Centre for IoT and Telecommunications, The University of Sydney. Prior to this role, he was with The School of Electrical Engineering and Computing, The University of Newcastle as a Research Fellow in Error Control Coding, where he currently holds a conjoint position. He received his PhD in Electrical Engineering (Telecommunications) from The University of Sydney in 2015 with The University of Sydney Postgraduate Award and Norman I Prize. He received MSc and BSc both in Electrical Engineering with 1st Class Honor in 2010 and 2008, respectively, from the Sharif University of Technology and University of Tehran. Dr Shirvanimoghaddam was selected as one of the Top 50 Young Scientists in the World by the World Economic Forum in 2018 for his contribution to the 4th Industrial Revolution. His research interests include Coding and Information Theory, Rateless coding, Communication strategies for the Internet of Things, and Information-theoretic approaches to Machine Learning. He is an IEEE Senior Member and a Fellow of the Higher Education Academy.
Address:Australia