Prof. Manoj Saxena of Deen Dayal Upadhyaya College, University of Delhi

Scaling of the CMOS transistor design poses serious constrain to the electrostatic control of charge carriers in the channel region. This will adversely affect the device behaviour in terms of the severe short-channel effects (SCEs) such as threshold voltage roll-off and hot carrier effects. To overcome the significant problem associated with the nanoscale MOSFET architecture, double gate junctionless (DG-JL) transistor has emerged as a potential candidate. As the current flow is mainly concentrated at the centre of film, surface scattering is very less which increases mobility and hence current drive in Single Material Double Gate JL transistor. In order to improve the transconductance, on-state current and gate-controllability over the channel, Dual Material DG-JL Transistor design was proposed. In the present talk, I shall be focusing on development of analytical model of drain current for Dual Material DG-JL Transistor. In the later part of my talk, I shall be addressing the impact of Non-Uniform Doping on the Reliability of Double Gate JunctionLess Transistor.

Biography:

Manoj Saxena received M. Sc., and Ph.D. degrees in Electronics from University of Delhi, New Delhi, in 2000 and 2006 respectively. He is currently Professor in Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi, India. He has authored or co-authored 315 technical papers in international journals and conference proceedings and has delivered 30 EDS Distinguished Lectures. His areas of research are Mathematical Modeling and TCAD Simulation of Non-Classical MOSFET, Tunnel FET and HEMT designs. He received “Highly Valued Volunteer for 2011-2012 EDS Chapters in South Asia, IEEE Region 10” and has reviewed 195+ manuscripts (in last 8 years) for 70+ international Journals and conferences. He is a Fellow of the National Academy of Sciences India (the oldest Science Academy of India); a Fellow-The Institution of Electronics and Telecommunication Engineers (IETE), India and Optical Society of India, Member of the Institute of Physics (UK), and Member of Institution of Engineering and Technology (IET), UK. In past he has served IEEE in different capacities i.e. Vice-Chair– IEEE EDS SRC Region 10 (2015-2017); Secretary - IEEE Delhi Section (2019) and EDS Newsletter Regional Editor of the South East Asia (2015-2020). He is currently a Member of the IEEE EDS Board of Governer (2018-2021, 2021 - ); Associate Editor-in-Chief of IEEE EDS Newsletter (2021 - ); IEEE EDS Distinguished Lecturer (2016-), and Chairman - EDS Delhi Chapter (2022 - ).

Email:

Address:Deen Dayal Upadhyaya College, University of Delhi, Delhi, India