IEEE EDS TECHNICAL TALK "A low-jitter 2.46-4.92GHz Two-stage Clock Multiplier in TSMC 65nm CMOS"

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Title: A low-jitter 2.46-4.92GHz Two-stage Clock Multiplier in TSMC 65nm CMOS

 

Speaker: Saurabh Saxena,Assistant Professor, Department of EE, IIT Madras

 

Abstract: A low power and low jitter two-stage 2.46-4.92GHz clock multiplier using a 38.4MHz reference clock is proposed. The clock multiplier implements an 8X clock multiplication with a delay-locked loop and an edge combiner in the first stage. The regulated supply of the voltage-controlled delay line and edge combiner within the delay-locked loop limits the first stage clock multiplication voltage sensitivity. The first-stage output injection locks a pseudo-differential ring oscillator embedded in a frequency tracking loop, thereby achieving a 64-128X clock multiplication in the second stage. Fabricated in a 65 nm CMOS process, the first-stage clock multiplier achieves an integrated jitter 761 fs rms at 307.2MHz while consuming 2.5mW. The mismatch and offset induced systematic jitter is calibrated, giving -53.4 dBc reference spur at the first-stage output. The second stage injection-locked clock multiplier adds low random jitter to the first stage with total output jitter 825 fsrms at 4.92GHz, -28.2 dBc reference spur, and 3mW power consumption.


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  • IIT Roorkee, India
  • Roorkee, Uttaranchal
  • India
  • Building: Electronic and communication department
  • Room Number: E&ICT Room
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  Speakers

Dr. Saurabh Saxena Dr. Saurabh Saxena of Department of EE, IIT Madras

Topic:

A low-jitter 2.46-4.92GHz Two-stage Clock Multiplier in TSMC 65nm CMOS

Abstract: A low power and low jitter two-stage 2.46-4.92GHz clock multiplier using a 38.4MHz reference clock is proposed. The clock multiplier implements an 8X clock multiplication with a delay-locked loop and an edge combiner in the first stage. The regulated supply of the voltage-controlled delay line and edge combiner within the delay-locked loop limits the first stage clock multiplication voltage sensitivity. The first-stage output injection locks a pseudo-differential ring oscillator embedded in a frequency tracking loop, thereby achieving a 64-128X clock multiplication in the second stage. Fabricated in a 65 nm CMOS process, the first-stage clock multiplier achieves an integrated jitter 761 fs rms at 307.2MHz while consuming 2.5mW. The mismatch and offset induced systematic jitter is calibrated, giving -53.4 dBc reference spur at the first-stage output. The second stage injection-locked clock multiplier adds low random jitter to the first stage with total output jitter 825 fsrms at 4.92GHz, -28.2 dBc reference spur, and 3mW power consumption.

Biography:

Saurabh Saxena received his B.Tech. degree in electrical engineering and the M.Tech. degree in Microelectronics and VLSI design from IIT Madras, Chennai,  India, in 2009. He received his Ph.D. degree in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign in 2015. He is currently an Assistant Professor with the Department of Electrical Engineering, IIT Madras. His research group is developing circuits for low power, energy proportional and wide range, and full-duplex multi-Gbps serial links. The group also designs clock generators and serial links for the Indian Space Research Organization. Dr. Saxena has been the recipient of Early Career Research (ECR) award and Visvesvaraya young faculty research fellowship (YFRF) awarded by GoI

Address:Department of EE, IIT Madras, , Madras, Tamil Nadu, India




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Technical Talk A low-jitter 2.46-4.92GHz Two-stage Clock Multiplier in TSMC 65nm CMOS 858.97 KiB