IEEE CAS SBC/STB Front-End Design and Simulation Methodology using Cadence

#Mixed #Signal #Circuits #Current #Mirrors #Layouts #Simulation #CADENCE #EDA #tools
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The aim of this workshop is to provide hands-on experience on the state-of-the-art Cadence EDA tools for VLSI Design. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and Extraction. The workshop includes practice sessions on the Cadence design and simulation tools (Virtuoso, Spectre). The workshop will cover introduction to different EDA Tools and discussed the importance of Cadence EDA tool, introducing the Custom IC Flow, design entry in virtuoso (Schematic editor), the characteristics of transistors by changing different parameters like W/L ratios and variations in biasing the circuit etc. The workshop includes simulation of the circuit using spectre and different analysis transient such as DC, AC etc. followed by the introduction to layouts.


  Date and Time

  Location

  Hosts

  Registration


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  • E&ICT Room
  • ECE Department
  • Roorkee, Uttaranchal
  • India 247667
  • Building: IIT Roorkee
  • Contact Event Hosts

  Speakers

Ashutosh Yadav Ashutosh Yadav

Topic:

Front-End Design and Simulation Methodology using Cadence

Mixed-signal applications are among the fastest growing market segments in the electronics and semiconductor industry. From watching mobile digital TV to reading on your tablet to auto-pilot cars, consumers expect electronics to do more-in more places-than ever before. Driven by growth opportunities in mobile communication, networking, power management, automotive, medical, imaging, safety and security applications, many silicon vendors are refocusing their business on RF, high-performance analog and mixed-signal designs.

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Agenda

There will be 4 sessions each of 2.30 hrs.

Day 1 Session 1: 11.00 AM to 1.30 PM

Day 1 Session 2: 3.00 PM to 5.30 PM

Day 2 Session 1: 11.00 AM to 1.30 PM

Day 2 Session 2: 3.00 PM to 5.30 PM


  Media

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