I am affiliated with IECD group and Nano Research Facility (NRF) at IIT Delhi. I work in the area of integrated circuits (IC). These are the tiny chips that are at the heart of most of the electronics and related products, from watches to rockets! Microprocessors for powerful computers are the biggest of these ICs, containing billions of logic gates within an area of a few squared cm. These logic gates are comprised of MOS transistors or MOSFETs fabricated using silicon wafers and if extreme care was not taken in design of MOSFETs and logic circuits, temperature of a billion transistor chip was predicted to match that of the Sun! Due to huge demand and corresponding requirement from the semiconductor industry, modeling and characterization of CMOS devices and circuits has been a very active area of electronics research for the past six decades. The focus of my research is on analysis of performance degradation of state of the art CMOS due to static variability, ageing, and exposure to various radiations. I collaborate with various industries on their advanced CMOS logic and RF technologies, which are then subjected to specialized electrical measurements to observe their degradation response. This electrical response, once coded in form of a SPICE-based compact model, is vital to designing bigger circuits that eventually lead to products. My current research interest is in modeling and characterization of:

1.   Silicon based qubits and CMOS at cryogenic temperatures for quantum computation

2.   RF-CMOS devices and circuits for WiFi/5G/6G applications

3.   Reliability of CMOS and GaN-HEMT devices

4.   Radiation effects in CMOS