UPDATED: Energy-Efficient ADC Designs assisted by SAR ADCs

#integrated #circuits #adc #ic #ssc #analog-to-digital
Share

Since late 2000’s, SAR ADCs have become one of the most popular ADC architectures showing not only excellent energy efficiency but also competitive conversion speed owing to the digital-friendly compact structure and architectural evolution in deep submicron technologies. Being utilized as sub building blocks, SAR ADCs could also enhance the performance of other types of ADCs such as pipelined, delta-sigma, and even flash ADCs. This talk discusses how SAR ADCs could improve ADC performances with various architectural innovations.


  Date and Time

  Location

  Hosts

  Registration


  • Date: 08 Dec 2022
  • Time: 04:00 PM to 05:00 PM
  • All times are (UTC-07:00) Mountain Time (US & Canada)
  • Add_To_Calendar_icon Add Event to Calendar
If you are not a robot, please complete the ReCAPTCHA to display virtual attendance info.
  • Contact Event Host
  • Co-sponsored by Solid-State Circuits
  • Starts 28 September 2022 08:56 AM
  • Ends 08 December 2022 03:59 PM
  • All times are (UTC-07:00) Mountain Time (US & Canada)
  • No Admission Charge

  Speakers

Seung-Tak Ryu Seung-Tak Ryu

Topic:

Bringing Back Pipelined ADCs in the Era of SAR ADCs

While SAR ADCs have become one of the most successful ADC architectures over the past decade owing to the compactness and the power-efficiency in advanced CMOS processes, pipelined ADCs seem to be somewhat out of the designer’s attention. However, we still can find some recent designs reporting competitive performances, often with SAR ADCs as their sub stage, utilizing opamp-free residue amplifiers. As high-speed single channel ADCs is preferable for time-interleaving (TI) to reduce the number of channels, the pipelined architecture is likely to remain as one of the best suited ones in achieving both high resolution and high speed. With this perspective, this talk reviews the development history of the pipelined ADCs and introduces recent architectures including the single-amp dual-residue pipelined ADC.

Biography:

SEUNG-TAK RYU received the M.S. and Ph.D. degrees from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1999 and 2004, respectively.

From 2001 to 2002, he was with the University of California, San Diego, CA, USA, as a Visiting Researcher, sponsored through the Brain Korea 21 (BK21) Program. In 2004, he joined Samsung Electronics, Yongin, South Korea, where he was involved in mixed-signal IP development. From 2007 to 2009, he was with the Information and Communications University (ICU), Daejeon, as an Assistant Professor. He has been with the School of Electrical Engineering, KAIST, since 2009, where he is currently a Professor. His research interests include analog and mixed-signal IC design with an emphasis on data converters and sensors.

He is a member of TPCs of Asian Solid-State Circuits Conference (A-SSCC), the Custom Integrated Circuits Conference (CICC), and European Solid-State Circuits Conference (ESSCIRC). He has served on the Technical Program Committee (TPC) for the IEEE International Solid-State Circuits Conference (ISSCC) and also served as a Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC) twice. He is an Associate Editor of the IEEE SOLID-STATE CIRCUITS LETTERS (SSCL) since 2018 and a Distinguished Lecturer for the IEEE Solid-State Circuits Society (2021-2022).

Address:Daejeon, South Korea