Prof. Joseph Cavallaro of Center for Multimedia Communication, Dept. of Electrical and Computer Engineering, Rice University

Talk Abstract:

Wireless communication system concepts for beyond 5G towards 6G include a variety of advanced physical layer algorithms to provide high data rates and increased efficiency for emerging Smart City and Internet of Things devices. In this talk, I will provide updates on our recent work in this area. Wireless algorithms provide different challenges for real-time performance based on the tradeoffs between computation, communication, I/O bottlenecks and area, time, and power complexity. Large scale or Massive MIMO systems can provide many benefits for both uplink detection and downlink beamforming as the number of base station antennas increase. Similarly for error protection, channel coding, such as LDPC, can support high data rates in many channel conditions. At the radio frequency level, available spectrum limitations lead to digital pre-distortion (DPD) to improve power amplifier efficiency and transmission range while reducing out of band interference. These physical layer algorithms impose complex system organization challenges in the interconnection of many RF transceivers with multiple memory and computation units with various data rates within the system. Parallel numerical methods can be applied to tradeoff computational complexity with minimal effect on error rate performance. In this talk, we will focus on design tools for high level synthesis (HLS) to capture and express parallelism in wireless communication algorithms. HLS can be applied to FPGA and ASIC synthesis, however, there exist tradeoffs in the area required with flexibility and reuse of designs. This also includes the mapping to GPU and multicore systems for high-speed simulation and potential virtual radio access networks. There is current interest in the selective use of neural networks and machine learning in communication systems. This talk will include a discussion of computation testbeds and our 3DML project for Data, Design and Deployed Validation of machine learning for wireless applications. The Rice WARP and Argos prototype massive MIMO radio testbeds enable over-the-air evaluation of these physical layer algorithms and architectures. The talk will conclude with an update on the National Science Foundation Platforms for Advanced Wireless Research (PAWR) collaboration between universities and industry and the Utah-Rice POWDER-RENEW testbed.

Biography:

Joseph R. Cavallaro received the B.S. degree from the University of Pennsylvania, Philadelphia, Pa, in 1981, the M.S. degree from Princeton University, Princeton, NJ, in 1982, and the Ph.D. degree from Cornell University, Ithaca, NY, in 1988, all in electrical engineering. He is an IEEE Fellow for contributions to very large-scale integration (VLSI) architectures and algorithms for signal processing and wireless communications. From 1981 to 1983, he was with AT&T Bell Laboratories, Holmdel, NJ. In 1988, he joined the faculty of Rice University, Houston, TX, where he is currently a Professor of electrical and computer engineering and Associate Chair. His research interests include computer arithmetic, and DSP, GPU, FPGA, and VLSI architectures for applications in wireless communications. During the 1996–1997 academic year, he served at the US National Science Foundation as Director of the Prototyping Tools and Methodology Program. He was a Nokia Foundation Fellow and a Visiting Professor at the University of Oulu, Finland in 2005. He is currently the Director of the Center for Multimedia Communication at Rice University. He has been an advisory board member of the IEEE SPS TC on Design and Implementation of Signal Processing Systems and the Past Chair of the IEEE CASS TC on Circuits and Systems for Communications. He is currently a senior area editor for the IEEE Transactions on Signal Processing, an Associate Editor for the Springer Journal of Signal Processing Systems and served as a senior editor for IEEE Journal on Emerging and Selected Topics in Circuits and Systems from 2020 to 2022, as an Associate Editor from 2013 to 2017 for the IEEE Signal Processing Letters and the IEEE Transactions on Signal Processing. He was General/Program Co-chair of the 2003, 2004, and 2011 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), and General/Program Co-chair for the 2012, 2014 ACM/IEEE GLSVLSI conferences. At the IEEE SiPS workshop, he was TPC Co-Chair in 2016 and General Co-Chair in 2020 and 2021. At the IEEE Asilomar Conference on Signals, Systems, and Computers, he was TPC Chair in 2017 and General Chair in 2020. He served on the IEEE CAS Society Board of Governors during 2014.

Email:

Address:Center for Multimedia Communication, Dept. of Electrical and Computer Engineering, Rice University, , Houston, Texas, United States