HANDS ON SESSION: INTRODUCTION TO VERILOG HDL

#IEEEDay #webinar #day #jssaten #technology #technical #coding

IEEE Signal Processing Society JSSATE on 2^nd October 2022 conducted hand off session: Introduction to Verilog HDL under the guidance of Dr. BP Mishra (Chapter Advisor, IEEE SPS) and Dr. Arun Kumar G (HOD -ECE). The webinar was delivered by Mr. Vaibhav Mishra.

The event was hosted by Divyanshu Pandey (Chairperson, IEEE SPS).31 participants from various colleges attended the session. Mr. Vaibhav Mishra is a semiconductor professional and founder of Aujus technology and Pine Training Academy with 18+ years of experience.

The session started with the speaker explaining how Verilog HDL came into being and use of Verilog in the industry. One example was taken of a combinational circuit – Half Adder. The design of the half adder was explained by the speaker and the design and test bench code were written on EDA Playground and then simulation for the circuit was done. The same process was followed by the participants and they successfully simulated the design.

The same process was done for the second example of D Flip Flop. The session was concluded with a Q&A session with the speaker where the participants asked their questions and queries to the speaker.

Certificates were mailed to the participants who attended the webinar.