Dr. Armin Tajalli of University of Utah

Most of the existing circuit design methodologies are based on iterative methods, which are very time consuming and sometimes far from being really optimal. The process of analog circuit design is generally so complex that most of the designers rely on their own intuitions, to design and move toward an acceptable design by paving generally a long path of trial-and-errors. There are two dominant circuit design methodologies mainly used in academic institutions: (1) Inversion-Coefficient or INVCO method, and (2) Gm/IDS or GOVIDS approach. While INVCO method is more analytical, both approaches require extensive device characterizations in order to create a rich and comprehensive set of data-base describing device performance in all modes of operations and different device sizes. Meanwhile, designers need to develop their own optimization scripts to search through all possible design points and select the best fit for their application, as these methodologies are not supported by the EDA Tools. Moreover, there is little design insight provided by either of these two methods. Due to these issues, none of these methods are widely used in industry, where time to-market is extremely crucial.

In this seminar, a novel design methodology will be introduced, which lies somewhere in between the two approaches. Called C/IDS or CovIDS, the proposed design methodology requires prior knowledge on only few technology-dependent parameters, which are very easy to extract. Moreover, this approach provides comprehensive design insight and the flow can be automatized smoothly. Several examples will be provided to show effectiveness of the proposed algorithm for implementing energy and power efficient circuits. Moreover, a set of data points demonstrating how performance of analog circuits evolve with technology scaling will be demonstrated.

Biography:

Armin Tajalli (Senior Member, IEEE) received the B.S. degree in electrical engineering from the Sharif University of Technology, Tehran, Iran, in 1997, and the Ph.D. degree in electrical engineering from the Swiss Federal Institute of Technology, Lausanne, Switzerland, in 2010.,He was part of the initiating team and a Senior Analog Architect with Kandou Bus, Lausanne, Switzerland, where he is currently the Lead of the Research and Development Department. Since December 2017, he has been an Assistant Professor with the University of Utah, Salt Lake City, USA. He has authored or coauthored more than 90 articles in peer-reviewed journals and conferences and holds 40 patents.,Dr. Tajalli was the recipient of several awards, including The Best Paper Award in DesignCon (2016), PhD Prime Award at EPFL, Switzerland (2010), and IEEE AMD/CICC Scholarship (2009). He is currently a Technical Program Committee Member in the IEEE Custom Integrated Circuit Conference (CICC) and European Solid-State Circuit Conference (ESSCIRC), and an Associate Editor for the IEEE Transactions on VLSI Systems.

Email:

Dr. Kent Layton of onsemi

SAR ADCs have become popular in literature and industry due to their efficient operation and wide range of speeds.  SAR ADC speed is often limited by reference settling which is more pronounced during the early conversion cycles.  Introducing redundant codes can relax the requirements on reference settling and increase the overall speed of the SAR conversion cycle.  This presentation will look at practical and "simple" ways of implementing redundant codes in standard SAR architectures.

Biography:

Dr. Layton received B.S., M.S., and Ph.D. degrees in Electrical and Computer Engineering from Brigham Young University in 1999 (BS & MS) and 2007 (Ph.D.).  His focus in research and industry is any type of analog circuitry.  He holds 11 patents and has published/presented a similar number of papers. He currently works for onsemi and teaches occassionally as an adjuct faculty memeber at BYU.  His greatest claim to fame is his job security ensured by his nearly indecipherable schematics.

Email: