Many-core system-on-chip (SoC) architecture & design challenges & opportunities spanning edge devices to cloud computing systems in scaled CMOS process are presented. Key techniques for robust and variation-tolerant logic, embedded memory arrays and on-die interconnect fabrics are discussed. Fine-grain multi-voltage design and power management techniques, featuring integrated voltage regulators for wide dynamic voltage-frequency operating range and flexible platform power control across multi-threaded high-throughput near- threshold voltage (NTV) to single-threaded burst performance modes, are elucidated. Smart variation-aware workload mapping, runtime self-adaptation and error detection & recovery schemes to mitigate impacts of process-voltage-temperature (PVT) variations & aging, and achieve maximum performance under stringent thermal and energy constraints, are presented. Latest advances in design and process/package for realization of monolithic & heterogeneous 2D/3D-integrated compact, efficient, low supply noise, fine-grain, high-bandwidth & fast- response power converters & voltage regulators, essential for implementing intelligent system-level power management and adaptation schemes across hardware and software, are also highlighted. Real SoC examples are used to demonstrate leading-edge practical systems.

Vivek De is an Intel Fellow and Director of Circuit Technology Research in Intel Labs. He is responsible for providing strategic technical directions for long term research in future circuit technologies and leading energy efficiency research across the hardware stack. He has 295 publications in refereed international conferences and journals with a citation H-index of 79, and 227 patents issued with 32 more patents filed (pending). He received an Intel Achievement Award for his contributions to an integrated voltage regulator technology. He is the recipient of the 2019 IEEE Circuits and System Society (CASS) Charles A. Desoer Technical Achievement Award for “pioneering contributions to leading-edge performance and energy-efficient microprocessors & many-core system-on-chip (SoC) designs” and the 2020 IEEE Solid-State Circuits Society (SSCS) Industry Impact Award for “seminal impact and distinctive contributions to the field of solid-state circuits and the integrated circuits industry”. He received a Best Paper Award at the 1996 IEEE International ASIC Conference, and nominations for Best Paper Awards at the 2007 IEEE/ACM Design Automation Conference (DAC) and 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). He also co-authored a paper nominated for the Best Student Paper Award at the 2017 IEEE International Electron Devices Meeting (IEDM). One of his publications was recognized in the 2013 IEEE/ACM Design Automation Conference (DAC) as one of the "Top 10 Cited Papers in 50 Years of DAC". Another one of his publications received the “Most Frequently Cited Paper Award” in the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017. He received the 2017 Distinguished Alumnus Award from the Indian Institute of Technology (IIT) Madras. He received a B.Tech from IIT Madras, India, a MS from Duke University, Durham, North Carolina, and a PhD from Rensselaer Polytechnic Institute, Troy, New York, all in Electrical Engineering. He is a Fellow of the IEEE.