Dr. Keshab K. Parhi of University of California Irvine

This talk will present approaches to functional obfuscation where the functionality is hidden by
incorporating keys to a design such that the circuit only functions correctly if the key is correct. Various
modes are introduced such that only the correct key triggers the correct functionality of the chip. One goal
is to prevent foundries from manufacturing excess parts and third party vendors from selling in black
market. Another goal is to prevent theft of intellectual property. A third goal of obfuscation is to prevent
reverse engineering. I will introduce the notions of fixed and dynamic functional obfuscation. We will
show that the time to find the key by trial and error can be increased exponentially with respect to the
number of key bits with dynamic obfuscation. In the second part of the talk, I will discuss chip
authentication using physical unclonable functions (PUFs). These are small circuits that can exploit
manufacturing process variations to generate unique signatures of chips. These unique signatures, in the
form of challenge-response pairs, can be stored in a server and can be used to authenticate devices.
Various delay-based PUFs include multiplexer (MUX) PUF and ring-oscillator PUF. I will talk about
modeling both linear and nonlinear MUX PUFs. We will show that both hard and soft responses of linear
and nonlinear MUX PUFs can be modeled by artificial neural network. I will then talk about XOR PUFs
and feed-forward XOR PUFs that are more secure.

Biography:

Dr. Keshab K. Parhi received the B.Tech. degree from the Indian Institute of Technology (IIT),
Kharagpur, in 1982, the M.S.E.E. degree from the University of Pennsylvania, Philadelphia, in 1984, and
the Ph.D. degree from the University of California, Berkeley, in 1988. He has been with the University of
Minnesota, Minneapolis, since 1988, where he is currently Erwin A. Kelen Chair in Electrical
Engineering and Distinguished McKnight University Professor in the Department of Electrical and
Computer Engineering. He has published over 700 papers, is the inventor of 34 patents, and has authored
the textbook VLSI Digital Signal Processing Systems (John Wiley & Sons, 1999). His current research
addresses VLSI architecture design of machine learning systems, hardware security, data-driven
neuroscience and DNA computing. Dr. Parhi is the recipient of numerous awards including the 2017 Mac
Van Valkenburg award and the 2012 Charles A. Desoer Technical Achievement award from the IEEE
Circuits and Systems Society, the 2004 F. E. Terman award from the American Society of Engineering
Education, and the 2003 IEEE Kiyo Tomiyasu Technical Field Award. He received the 2013
Distinguished Alumnus award from the IIT Kharagpur. He has served as the Editor-in-Chief of the IEEE
Trans. Circuits and Systems, Part-I during 2004 and 2005. He is a Fellow of IEEE, ACM, AIMBE,
AAAS and the National Academy of Inventors.

Address:California, United States